Layout Minimization of CMOS Cells

Language: English

Published by Springer, Springer Okt 1991, 1991

0792391829 / 9780792391821

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This item is printed on demand - Print on Demand Titel. Neuware -The layout of an integrated circuit (lC) is the process of assigning geometric shape, size and position to the components (transistors and connections) used in its fabrication. Since the number of components in modem ICs is enormous, computer aided-design (CAD) programs are required to automate the difficult layout process. Prior CAD methods are inexact or limited in scope, and produce layouts whose area, and consequently manufacturing costs, are larger than necessary. This book addresses the problem of minimizing exactly the layout area of an important class of basic IC structures called CMOS cells. First, we precisely define the possible goals in area minimization for such cells, namely width and height minimization, with allowance for area-reducing reordering of transistors. We reformulate the layout problem in terms of a graph model and develop new graph-theoretic concepts that completely characterize the fundamental area minimization problems for series-parallel and nonseries-parallel circuits. These concepts lead to practical algorithms that solve all the basic layout minimization problems exactly, both for a single cell and for a one-dimensional array of such cells. Although a few of these layout problems have been solved or partially solved previously, we present here the first complete solutions to all the problems of interest.Springer-Verlag KG, Sachsenplatz 4-6, 1201 Wien 188 pp. Englisch.

Seller Inventory # 9780792391821

Title
Layout Minimization of CMOS Cells
Author
Robert L. Maziasz
Publisher
Springer, Springer Okt 1991
Publication year
1991
Condition
Neu
Binding
Buch
Language
English
ISBN 10
0792391829
ISBN 13
9780792391821
Item weight
453 grams
Dimensions
241x160x15 mm

buchversandmimpf2000

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