Logic Synthesis for Low Power VLSI Designs

Sasan Iman

ISBN 10: 0792380762 / ISBN 13: 9780792380764

Published by Springer US, Springer New York Nov 1997, 1997

About this Item

Neuware -Logic Synthesis for Low Power VLSI Designs presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. More precisely, this book provides a detailed presentation of methodologies, algorithms and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. Logic Synthesis for Low Power VLSI Designs contains detailed descriptions of technology-dependent logic transformations and optimizations, technology decomposition and mapping, and post-mapping structural optimization techniques for low power. It also emphasizes the trade-off techniques for two-level and multi-level logic circuits that involve power dissipation and circuit speed, in the hope that the readers can better understand the issues and ways of achieving their power dissipation goal while meeting the timing constraints.Logic Synthesis for Low Power VLSI Designs is written for VLSI design engineers, CAD professionals, and students who have had a basic knowledge of CMOS digital design and logic synthesis.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 256 pp. Englisch.

Seller Inventory # 9780792380764

Bibliographic Details

• Title: Logic Synthesis for Low Power VLSI Designs
• Publisher: Springer US, Springer New York Nov 1997
• Publication Date: 1997
• Language: English
• ISBN 10: 0792380762
• ISBN 13: 9780792380764
• Binding: Buch
• Condition: Neu
• Dimensions: 241W x 160H x 20D millimeters 241 millimeters width by 160 millimeters height by 20 millimeters depth
• Weight: 551 grams

About this title

Synopsis

Logic Synthesis for Low Power VLSI Designs presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. More precisely, this book provides a detailed presentation of methodologies, algorithms and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. Logic Synthesis for Low Power VLSI Designs contains detailed descriptions of technology-dependent logic transformations and optimizations, technology decomposition and mapping, and post-mapping structural optimization techniques for low power. It also emphasizes the trade-off techniques for two-level and multi-level logic circuits that involve power dissipation and circuit speed, in the hope that the readers can better understand the issues and ways of achieving their power dissipation goal while meeting the timing constraints.
Logic Synthesis for Low Power VLSI Designs is written for VLSI design engineers, CAD professionals, and students who have had a basic knowledge of CMOS digital design and logic synthesis.