Sasan Iman (40 results)

Hardcover. Condition: Good. Connecting readers with great books since 1972! Used textbooks may not include companion materials such as access codes, etc. May have some wear or writing/highlighting. We ship orders daily and Customer Service is our top priority.

hardcover. Condition: Good. Connecting readers with great books since 1972! Used textbooks may not include companion materials such as access codes, etc. May have some wear or writing/highlighting. We ship orders daily and Customer Service is our top priority.

Condition: Very Good. 1st. Pages intact with possible writing/highlighting. Binding strong with minor wear. Dust jackets/supplements may not be included. Stock photo provided. Product includes identifying sticker. Better World Books: Buy Books. Do Good.

hardcover. Condition: Very Good. No Dust Jacket. Name from previous owner on FEP. No dust jacket. Binding is very well preserved, pages clean and and crisp, and printing is tight, clean and bright throughout. Not noticeably different from like new. MB. Used.

Condition: DISCRETO USATO. Da revisionare INGLESE Legatura dalla copertina in robusto cartonato con pigmento appesantito dalla luce, segnato da manipolazione o attrito, impronte da uso e patinato in parte arricciato, interno molto ben preservato, denso pulviscolo da muffe ai tagli. N. pag. 349.

Condition: New. In English.

Condition: New. In English.

Taschenbuch. Condition: Neu. Logic Synthesis for Low Power VLSI Designs | Sasan Iman (u. a.) | Taschenbuch | xv | Englisch | 2012 | Springer | EAN 9781461374909 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu.…

Condition: New. Provides detailed presentations of methodologies, algorithms and CAD tools for power modelling, estimation and analysis, synthesis and optimization at the logic level. It is designed for engineers, CAD professionals, and students with a basic knowledge of CMOS digital design and logic synthesis. Num Pages: 236 pages, biography. BIC Classification: TJF; UK. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly; (UU) Undergraduate. Dimension: 234 x 156 x 15. Weight in Grams: 1190. . 1997. Hardback. . . . .…

hardcover. Condition: New. In shrink wrap. Looks like an interesting title.

Condition: New. pp. 258.

Condition: New.

Condition: New. pp. 256.

Condition: New.

Condition: As New. Unread book in perfect condition.

Condition: As New. Unread book in perfect condition.

Condition: New. In English.

Condition: New. In English.

Condition: New. Provides detailed presentations of methodologies, algorithms and CAD tools for power modelling, estimation and analysis, synthesis and optimization at the logic level. It is designed for engineers, CAD professionals, and students with a basic knowledge of CMOS digital design and logic synthesis. Num Pages: 236 pages, biography. BIC Classification: TJF; UK. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly; (UU) Undergraduate. Dimension: 234 x 156 x 15. Weight in Grams: 1190. . 1997. Hardback. . . . . Books ship from the US and Ireland.…

Buch. Condition: Neu. Druck auf Anfrage Neuware - Printed after ordering - I am glad to see this new book on the e language and on verification. I am especially glad to see a description of the e Reuse Methodology (eRM). The main goal of verification is, after all, finding more bugs quicker using given resources, and verification reuse (module-to-system, old-system-to-new-system etc. ) is a key enabling component. This book offers a fresh approach in teaching the e hardware verification language within the context of coverage driven verification methodology. I hope it will help the reader und- stand the many important and interesting topics surrounding hardware verification. Yoav Hollander Founder and CTO, Verisity Inc. Preface This book provides a detailed coverage of the e hardware verification language (HVL), state of the art verification methodologies, and the use of e HVL as a facilitating verification tool in implementing a state of the art verification environment. It includes comprehensive descriptions of the new concepts introduced by the e language, e language syntax, and its as- ciated semantics. This book also describes the architectural views and requirements of verifi- tion environments (randomly generated environments, coverage driven verification environments, etc. ), verification blocks in the architectural views (i. e. generators, initiators, c- lectors, checkers, monitors, coverage definitions, etc. ) and their implementations using the e HVL. Moreover, the e Reuse Methodology (eRM), the motivation for defining such a gui- line, and step-by-step instructions for building an eRM compliant e Verification Component (eVC) are also discussed.…

Condition: New. pp. 376.

Condition: New. pp. 380.

Paperback. Condition: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.

Paperback. Condition: Brand New. reprint edition. 371 pages. 9.25x6.10x0.85 inches. In Stock.

Hardcover. Condition: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.

Hardcover. Condition: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.

Condition: new. Questo è un articolo print on demand.

Gebunden. Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Logic Synthesis for Low Power VLSI Designs presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. More precisely, this book provides a detailed presentation of methodologies, algorithms and CAD t.…

Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Logic Synthesis for Low Power VLSI Designs presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. More precisely, this book provides a detailed presentation of methodologies, algorithms and CAD t.…

Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Logic Synthesis for Low Power VLSI Designs presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. More precisely, this book provides a detailed presentation of methodologies, algorithms and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. Logic Synthesis for Low Power VLSI Designs contains detailed descriptions of technology-dependent logic transformations and optimizations, technology decomposition and mapping, and post-mapping structural optimization techniques for low power. It also emphasizes the trade-off techniques for two-level and multi-level logic circuits that involve power dissipation and circuit speed, in the hope that the readers can better understand the issues and ways of achieving their power dissipation goal while meeting the timing constraints.Logic Synthesis for Low Power VLSI Designs is written for VLSI design engineers, CAD professionals, and students who have had a basic knowledge of CMOS digital design and logic synthesis.Springer-Verlag KG, Sachsenplatz 4-6, 1201 Wien 256 pp. Englisch.…