Low Leakage SRAM Memory | Design of Low Power High Performance SRAMMemory using Gate Leakage ReductionTechnique

Debasis Mukherjee

ISBN 10: 6205517116 / ISBN 13: 9786205517116

Published by LAP LAMBERT Academic Publishing, 2022

About this Item

Low Leakage SRAM Memory | Design of Low Power High Performance SRAMMemory using Gate Leakage ReductionTechnique | Debasis Mukherjee | Taschenbuch | Englisch | 2022 | LAP LAMBERT Academic Publishing | EAN 9786205517116 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu.

Seller Inventory # 126187511

Bibliographic Details

• Title: Low Leakage SRAM Memory | Design of Low Power High Performance SRAMMemory using Gate Leakage ReductionTechnique
• Publisher: LAP LAMBERT Academic Publishing
• Publication Date: 2022
• Language: English
• ISBN 10: 6205517116
• ISBN 13: 9786205517116
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 220W x 150H x 5D millimeters 220 millimeters width by 150 millimeters height by 5 millimeters depth
• Weight: 119 grams
• Seller catalogs:
  • Bücher

About this title

Synopsis

I present some techniques to decrease the gate and other leakage dissipation in Deep Sub-Micron SRAM memories. This book reviews detail SRAM operations. This book also reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Finally, the book explores different circuit techniques to reduce the leakage power consumption. The W/L ratios are calculated from the equations of current in transistors (Linear and Saturation mode) for smooth read-write operation of both 0 and 1. I use W1/W3 = 1.5 and W4/W6 = 1.5. I first designed conventional SRAM memory and observed leakage current in various technology. In 90 nm technology conventional SRAM shows a leakage current of 1.87nA at steady state. Data retention gated-ground cache (DGR-cache) method reduces the leakage current to 100pA. Drowsy cache method reduces the leakage current to 84pA.