Low Power Asynchronous Logic design for Viterbi Decoders

Language: English

Published by LAP LAMBERT Academic Publishing Sep 2018, 2018

6139851297 / 9786139851294

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Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermanyBuchWeltWeit Ludwig Meier e.K.

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This item is printed on demand - it takes 3-4 days longer - Neuware -This book discusses the design of asynchronous logic and its importance in digital design. Most of the decoders designed and fabricated today are synchronous. The problem of clock skew is a major challenge in the synchronous design. Alternatively, asynchronous systems are becoming familiar as they are not in need of global clock, as these systems are locally synchronized by means of communication protocols. Asynchronous VLSI architecture for a Viterbi decoder is designed using Quasi Delay Insensitive (QDI) templates and Differential Cascode Voltage Switch Logic (DCVSL). It gives an overview of asynchronous implementation. 56 pp. Englisch.

Seller Inventory # 9786139851294

Title
Low Power Asynchronous Logic design for Viterbi Decoders
Author
T. Kalavathi Devi Sakthivel
Publisher
LAP LAMBERT Academic Publishing Sep 2018
Publication year
2018
Condition
Neu
Binding
Taschenbuch
Language
English
ISBN 10
6139851297
ISBN 13
9786139851294
Item weight
102 grams
Dimensions
220x150x4 mm

BuchWeltWeit Ludwig Meier e.K.

Bergisch Gladbach, Germany

5-star seller

AbeBooks seller since January 11, 2012

Shipping rates from Germany to U.S.A.

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BuchWeltWeit Ludwig Meier e.K.

Germany