Low-power Deep Sub-micron Cmos Logic : Sub-threshold Current Reduction
Meer, P.; Van Staveren, A.; Roermund, Arthur H. M.
ISBN 10: 1475710577 ISBN 13: 9781475710571
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1. 1 Power-dissipation trends in CMOS circuits Shrinking device geometry, growing chip area and increased data-processing speed performance are technological trends in the integrated circuit industry to enlarge chip functionality. Already in 1965 Gordon Moore predicted that the total number of devices on a chip would double every year until the 1970s and every 24 months in the 1980s. This prediction is widely known as "Moore's Law" and eventually culminated in the Semiconductor Industry Association (SIA) technology road map [1]. The SIA road map has been a guide for the in dustry leading them to continued wafer and die size growth, increased transistor density and operating frequencies, and defect density reduction. To mention a few numbers; the die size increased 7% per year, the smallest feature sizes decreased 30% and the operating frequencies doubled every two years. As a consequence of these trends both the number of transistors and the power dissi pation per unit area increase.In the near future the maximum power dissipation per unit area will be reached. Down-scaling of the supply voltage is not only the most effective way to reduce power dissipation in general it also is a necessary precondition to ensure device reliability by reducing electrical fields and device temperature, to prevent device degradation. A draw-back of this solution is an increased signal propa gation delay, which results in a lower data-processing speed performance.
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Title: Low-power Deep Sub-micron Cmos Logic : ...
Publisher: Springer
Publication Date: 2012
Binding: Soft cover
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Low-Power Deep Sub-Micron CMOS Logic (eng)
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Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Classifies all power dissipation sources in digital CMOS circuitsProvides for a systematic approach of power reduction techniquesA clear distinction between power dissipated to perform a calculation in a certain time frame, i.e. functional . Seller Inventory # 4206973
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Low-Power Deep Sub-Micron CMOS Logic | Sub-threshold Current Reduction
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Taschenbuch. Condition: Neu. Low-Power Deep Sub-Micron CMOS Logic | Sub-threshold Current Reduction | P. van der Meer (u. a.) | Taschenbuch | The Springer International Series in Engineering and Computer Science | xiv | Englisch | 2012 | Springer | EAN 9781475710571 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu. Seller Inventory # 105720512
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Low-Power Deep Sub-Micron CMOS Logic
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Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -1. 1 Power-dissipation trends in CMOS circuits Shrinking device geometry, growing chip area and increased data-processing speed performance are technological trends in the integrated circuit industry to enlarge chip functionality. Already in 1965 Gordon Moore predicted that the total number of devices on a chip would double every year until the 1970s and every 24 months in the 1980s. This prediction is widely known as 'Moore's Law' and eventually culminated in the Semiconductor Industry Association (SIA) technology road map [1]. The SIA road map has been a guide for the in dustry leading them to continued wafer and die size growth, increased transistor density and operating frequencies, and defect density reduction. To mention a few numbers; the die size increased 7% per year, the smallest feature sizes decreased 30% and the operating frequencies doubled every two years. As a consequence of these trends both the number of transistors and the power dissi pation per unit area increase.In the near future the maximum power dissipation per unit area will be reached. Down-scaling of the supply voltage is not only the most effective way to reduce power dissipation in general it also is a necessary precondition to ensure device reliability by reducing electrical fields and device temperature, to prevent device degradation. A draw-back of this solution is an increased signal propa gation delay, which results in a lower data-processing speed performance.Springer-Verlag KG, Sachsenplatz 4-6, 1201 Wien 172 pp. Englisch. Seller Inventory # 9781475710571
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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -1. 1 Power-dissipation trends in CMOS circuits Shrinking device geometry, growing chip area and increased data-processing speed performance are technological trends in the integrated circuit industry to enlarge chip functionality. Already in 1965 Gordon Moore predicted that the total number of devices on a chip would double every year until the 1970s and every 24 months in the 1980s. This prediction is widely known as 'Moore's Law' and eventually culminated in the Semiconductor Industry Association (SIA) technology road map [1]. The SIA road map has been a guide for the in dustry leading them to continued wafer and die size growth, increased transistor density and operating frequencies, and defect density reduction. To mention a few numbers; the die size increased 7% per year, the smallest feature sizes decreased 30% and the operating frequencies doubled every two years. As a consequence of these trends both the number of transistors and the power dissi pation per unit area increase.In the near future the maximum power dissipation per unit area will be reached. Down-scaling of the supply voltage is not only the most effective way to reduce power dissipation in general it also is a necessary precondition to ensure device reliability by reducing electrical fields and device temperature, to prevent device degradation. A draw-back of this solution is an increased signal propa gation delay, which results in a lower data-processing speed performance. 172 pp. Englisch. Seller Inventory # 9781475710571
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Low-Power Deep Sub-Micron Cmos Logic (The Springer International Series in Engineering and Computer Science)
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Low-Power Deep Sub-Micron CMOS Logic : Sub-threshold Current Reduction
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Taschenbuch. Condition: Neu. Druck auf Anfrage Neuware - Printed after ordering - 1. 1 Power-dissipation trends in CMOS circuits Shrinking device geometry, growing chip area and increased data-processing speed performance are technological trends in the integrated circuit industry to enlarge chip functionality. Already in 1965 Gordon Moore predicted that the total number of devices on a chip would double every year until the 1970s and every 24 months in the 1980s. This prediction is widely known as 'Moore's Law' and eventually culminated in the Semiconductor Industry Association (SIA) technology road map [1]. The SIA road map has been a guide for the in dustry leading them to continued wafer and die size growth, increased transistor density and operating frequencies, and defect density reduction. To mention a few numbers; the die size increased 7% per year, the smallest feature sizes decreased 30% and the operating frequencies doubled every two years. As a consequence of these trends both the number of transistors and the power dissi pation per unit area increase.In the near future the maximum power dissipation per unit area will be reached. Down-scaling of the supply voltage is not only the most effective way to reduce power dissipation in general it also is a necessary precondition to ensure device reliability by reducing electrical fields and device temperature, to prevent device degradation. A draw-back of this solution is an increased signal propa gation delay, which results in a lower data-processing speed performance. Seller Inventory # 9781475710571
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Low-Power Deep Sub-Micron CMOS Logic: Sub-threshold Current Reduction (The Springer International Series in Engineering and Computer Science (841))
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