Title: Lower Bounds on Vlsi Implementations of Communication Networks May 1981 Classic Reprint
Publisher: Forgotten Books
Publication Date: 2019
Language: English
ISBN 10: 0656943432
ISBN 13: 9780656943432
Binding: HRD
Condition: New
Weight: 268 grams

About this title

Synopsis

Understanding how network structure shapes chip area and performance

This book examines how communication networks can be implemented on VLSI chips. It explains how network topologies, such as permutation networks and concentrators, affect the physical area required and the achievable performance. The discussion covers both traditional circuit-switching networks and packet-switching approaches, with a focus on lower bounds that guide what is possible in practice.

Two sections analyze how to model and measure network efficiency. One shows that certain networks require area growing with the square of the number of inputs and outputs, while others can achieve linear growth in lines and switches but still face area limits. The other section develops ideas about bisection width, routing, and bandwidth, linking them to realistic 3D and planar implementations. The material also connects these concepts to universal ultracomputers, where many processors coordinate by message exchange over the network.

Grasp common network families like n-permutation networks, n-superconcentrators, and n-hyperconcentrators, and how they relate to area bounds.
Learn how bisection width and bandwidth influence the minimal area of both packet-switching and circuit-switching networks.
See how 3D layout and recirculating networks change the scaling of area with respect to size and performance.
Understand how planning routing strategies, whether centralized or decentralized, affects network efficiency and lower bounds.

Ideal for readers who want a practical, theory-grounded view of how network design impacts hardware size and performance in VLSI systems.

"About this title" may belong to another edition of this title.

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