3D Networks-on-Chip Architecture Optimization for Low Power Design

Michael Opoku Agyeman

ISBN 10: 3659758132 / ISBN 13: 9783659758133

Published by LAP LAMBERT Academic Publishing, 2015

About this Item

3D Networks-on-Chip Architecture Optimization for Low Power Design | Michael Opoku Agyeman | Taschenbuch | 180 S. | Englisch | 2015 | LAP LAMBERT Academic Publishing | EAN 9783659758133 | Verantwortliche Person für die EU: BoD - Books on Demand, In de Tarpen 42, 22848 Norderstedt, info[at]bod[dot]de | Anbieter: preigu.

Seller Inventory # 104318174

Bibliographic Details

• Title: 3D Networks-on-Chip Architecture Optimization for Low Power Design
• Publisher: LAP LAMBERT Academic Publishing
• Publication Date: 2015
• Language: English
• ISBN 10: 3659758132
• ISBN 13: 9783659758133
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 220W x 150H x 11D millimeters 220 millimeters width by 150 millimeters height by 11 millimeters depth
• Weight: 286 grams
• Seller catalogs:
  • Bücher

About this title

Synopsis

Three dimensional Networks-on-Chip (3D NoCs) have attracted a growing interest to solve on-chip communication demands of future multi-core embedded systems. However, 3D NoCs have not been completely accepted into the mainstream due to issues such as the high cost and complexity of manufacturing 3D vertical wires, larger memory, area and power consumption of 3D NoC components than that of conventional 2D NoC. This thesis aims at optimizing 3D NoCs by modeling and evaluating alternate NoC topologies, routing algorithms and mapping techniques to achieve optimized area, power and performance parameters (latency and throughput). Particularly, novel 3D NoC router architectures and their possible combinations have been investigated with the aim of achieving lower area and power consumption of on-chip communication components with a minimal performance trade-off. This book investigates different heterogeneous 3D NoC architectures which combine 2D and 3D routers to improve area and energy efficiency of 3D NoCs with minimal performance degradation.

About the Author

Dr Michael Opoku Agyeman received the BSc. (Hons.) in electrical and electronics engineering from KNUST, Ghana, in 2008, and the MSc. degree in embedded and distributed systems from LSBU, London, in 2009. He received the PhD from the department of computing at Glasgow Caledonian University, Glasgow, in 2014.