Optimal VLSI Architectural Synthesis: Area, Performance and Testability (The Springer International Series in Engineering and Computer Scien

Catherine H. Gebotys et Mohamed I. Elmasry

ISBN 10: 079239223X / ISBN 13: 9780792392231

Published by Springer, 1991

About this Item

Ancien livre de bibliothèque. Légères traces d'usure sur la couverture. Edition 1991. Ammareal reverse jusqu'à 15% du prix net de cet article à des organisations caritatives. ENGLISH DESCRIPTION Book Condition: Used, Very good. Former library book. Slight signs of wear on the cover. Edition 1991. Ammareal gives back up to 15% of this item's net price to charity organizations.

Seller Inventory # D-706-848

Bibliographic Details

• Title: Optimal VLSI Architectural Synthesis: Area, Performance and Testability (The Springer International Series in Engineering and Computer Scien
• Publisher: Springer
• Publication Date: 1991
• Language: English
• ISBN 10: 079239223X
• ISBN 13: 9780792392231
• Binding: Hardcover
• Condition: Très bon

About this title

Synopsis

Although research in architectural synthesis has been conducted for over ten years it has had very little impact on industry. This in our view is due to the inability of current architectural synthesizers to provide area-delay competitive (or "optimal") architectures, that will support interfaces to analog, asynchronous, and other complex processes. They also fail to incorporate testability. The OASIC (optimal architectural synthesis with interface constraints) architectural synthesizer and the CATREE (computer aided trees) synthesizer demonstrate how these problems can be solved. Traditionally architectural synthesis is viewed as NP hard and there­ fore most research has involved heuristics. OASIC demonstrates by using an IP approach (using polyhedral analysis), that most input algo­ rithms can be synthesized very fast into globally optimal architectures. Since a mathematical model is used, complex interface constraints can easily be incorporated and solved. Research in test incorporation has in general been separate from syn­ thesis research. This is due to the fact that traditional test research has been at the gate or lower level of design representation. Nevertheless as technologies scale down, and complexity of design scales up, the push for reducing testing times is increased. On way to deal with this is to incorporate test strategies early in the design process. The second half of this text examines an approach for integrating architectural synthesis with test incorporation. Research showed that test must be considered during synthesis to provide good architectural solutions which minimize Xlll area delay cost functions.