Optimal VLSI Architectural Synthesis: Area Performance and Testability

Gebotys, Catherine H.; Elmasry, Mohamed I.

ISBN 10: 079239223X / ISBN 13: 9780792392231

Published by Kluwer Academic Publishers, Boston, 1991

About this Item

Hardcover in very good condition. No jacket. Boards are lightly marked. Leading corners and spine ends are lightly bumped and worn. Previous owner's name penned on FEP. Pages are clean and contents are clear throughout. HCW.

Seller Inventory # 248214

Bibliographic Details

• Title: Optimal VLSI Architectural Synthesis: Area Performance and Testability
• Publisher: Kluwer Academic Publishers, Boston
• Publication Date: 1991
• Language: English
• ISBN 10: 079239223X
• ISBN 13: 9780792392231
• Binding: hardcover
• Condition: Very Good
• Dust Jacket Condition: No Dust Jacket
• Book Type: Used
• Seller catalogs:
  • Science - Electronics

About this title

Synopsis

Although research in architectural synthesis has been conducted for over ten years it has had very little impact on industry. This in our view is due to the inability of current architectural synthesizers to provide area-delay competitive (or "optimal") architectures, that will support interfaces to analog, asynchronous, and other complex processes. They also fail to incorporate testability. The OASIC (optimal architectural synthesis with interface constraints) architectural synthesizer and the CATREE (computer aided trees) synthesizer demonstrate how these problems can be solved. Traditionally architectural synthesis is viewed as NP hard and there­ fore most research has involved heuristics. OASIC demonstrates by using an IP approach (using polyhedral analysis), that most input algo­ rithms can be synthesized very fast into globally optimal architectures. Since a mathematical model is used, complex interface constraints can easily be incorporated and solved. Research in test incorporation has in general been separate from syn­ thesis research. This is due to the fact that traditional test research has been at the gate or lower level of design representation. Nevertheless as technologies scale down, and complexity of design scales up, the push for reducing testing times is increased. On way to deal with this is to incorporate test strategies early in the design process. The second half of this text examines an approach for integrating architectural synthesis with test incorporation. Research showed that test must be considered during synthesis to provide good architectural solutions which minimize Xlll area delay cost functions.