Performance Evaluation of 3D SRAM Architecture using Coaxial TSV | Research Perspective

R. Arun Prasath (u. a.)

ISBN 10: 3659746495 / ISBN 13: 9783659746499

Published by LAP Lambert Academic Publishing, 2015

About this Item

Performance Evaluation of 3D SRAM Architecture using Coaxial TSV | Research Perspective | R. Arun Prasath (u. a.) | Taschenbuch | 68 S. | Englisch | 2015 | LAP Lambert Academic Publishing | EAN 9783659746499 | Verantwortliche Person für die EU: BoD - Books on Demand, In de Tarpen 42, 22848 Norderstedt, info[at]bod[dot]de | Anbieter: preigu.

Seller Inventory # 104436321

Bibliographic Details

• Title: Performance Evaluation of 3D SRAM Architecture using Coaxial TSV | Research Perspective
• Publisher: LAP Lambert Academic Publishing
• Publication Date: 2015
• Language: English
• ISBN 10: 3659746495
• ISBN 13: 9783659746499
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 220W x 150H x 5D millimeters 220 millimeters width by 150 millimeters height by 5 millimeters depth
• Weight: 119 grams
• Seller catalogs:
  • Bücher

About this title

Synopsis

3D stacking of logic and memory devices is essential to keep the Moore's law ticking. In 3D integration, memory devices can be stacked on the top of processors. TSV based 3D memory architecture enables the reuse of logic dies with multiple memory layers. Conventional 3D memory suffer from speed, power and yield overhead due to large parasitic load of TSV and cross layer PVT variations. In order to overcome these limitations, this paper the physical design of a semi master-slave (SMS) architecture of 3D SRAM which provides a constant-load logic-SRAM interface across various stacked layers and high tolerance for variations in cross-layer PVT is introduced. The SMS scheme is combined with self-timed differential-TSV (STDT) employing a TSV-load tracking scheme to achieve small TSV voltage swing for suppressing power and speed overheads of cross-layer TSV signal communication resulting from large TSV parasitic loads in UMCP designs with scalable stacked layers and wide IO. This provides a universal memory capacity platform.