Performance Optimization in Network-on-Chip: Multi Level Network Partitioning Approach

Edanan, Muhamad Qaedi/ Lit, Asrani

ISBN 10: 3659907456 / ISBN 13: 9783659907456

Published by LAP LAMBERT Academic Publishing, 2016

About this Item

80 pages. 8.66x5.91x0.19 inches. In Stock.

Seller Inventory # 3659907456

Bibliographic Details

• Title: Performance Optimization in Network-on-Chip: Multi Level Network Partitioning Approach
• Publisher: LAP LAMBERT Academic Publishing
• Publication Date: 2016
• Language: English
• ISBN 10: 3659907456
• ISBN 13: 9783659907456
• Binding: Paperback
• Condition: Brand New
• Weight: 0.17 kilograms

About this title

Synopsis

The increasing complexity of System-on-Chips (SoCs) has resulted in the bottlenecking of the system due to scalability problems in the bus system. This leads to the decrement of performance of future SoCs with more complex circuitries inside them. Network-on-Chips (NoCs) was proposed as one of the solutions to overcome these issues especially regarding the communication between Intellectual Properties (IP) in a chip. The fundamentals in designing NoC include the selection of network topologies, and hence, performance optimization is needed to ensure the full advantage of networking is taken. Therefore, multi-level Network Partitioning techniques are proposed to obtain the optimal design of networks based on its performance. The performance of a network is measured by its throughput, average queue size, waiting time and data loss. This technique is applied in a case study using MPEG-4 video application. The proposed technique is expected to enhance the performance of the NoC.

About the Author

Muhamad Qaedi Edanan is a Bachelor in Electronic Engineering (Computer) from Universiti Malaysia Sarawak (UNIMAS). Asrani Lit is a Research Scientist at Department of Electrical and Electronic in UNIMAS.