A Pipelined Multi-core MIPS Machine

Mikhail Kovalev

ISBN 10: 3319139053 / ISBN 13: 9783319139050

Published by Springer, Springer Dez 2014, 2014

About this Item

This item is printed on demand - Print on Demand Titel. Neuware -This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory.The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially consistent shared memory. This opens the way to the formal verification of synthesizable hardware for multi-core processors in the future.Constructions are in a gate level hardware model and thus deterministic. In contrast the reference models against which correctness is shown are nondeterministic. The development of the additional machinery for these proofs and the correctness proof of the shared memory at the gate level are the main technical contributions of this work.Springer-Verlag KG, Sachsenplatz 4-6, 1201 Wien 364 pp. Englisch.

Seller Inventory # 9783319139050

Bibliographic Details

• Title: A Pipelined Multi-core MIPS Machine
• Publisher: Springer, Springer Dez 2014
• Publication Date: 2014
• Language: English
• ISBN 10: 3319139053
• ISBN 13: 9783319139050
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 235W x 155H x 20D millimeters 235 millimeters width by 155 millimeters height by 20 millimeters depth
• Weight: 552 grams

About this title

Synopsis

This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory.

The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially consistent shared memory. This opens the way to the formal verification of synthesizable hardware for multi-core processors in the future.

Constructions are in a gate level hardware model and thus deterministic. In contrast the reference models against which correctness is shown are nondeterministic. The development of the additional machinery for these proofs and the correctness proof of the shared memory at the gate level are the main technical contributions of this work.