Process Variation Tolerant VLSI Designs : Highly Robust and Process Variation Tolerant CMOS Dynamic Logic Designs

Vikas Mahor

ISBN 10: 3659648949 / ISBN 13: 9783659648946

Published by LAP LAMBERT Academic Publishing, 2014

About this Item

nach der Bestellung gedruckt Neuware - Printed after ordering - Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise margin compared to that of standard CMOS gates. Traditionally, this issue has been resolved by employing a pMOS keeper circuit that compensates for leakage current of the pull-down nMOS network. In the earlier technology nodes, the keeper circuit could improve reliability of the dynamic gates with minor performance penalty. However, aggressive scaling trends of CMOS technology along with increasing levels of process variations have reduced effectiveness of the traditional keeper approach. This problem is more severe in wide fan-in dynamic gates due to the large number of leaky nMOS devices connected to the dynamic node. In this work a process variation tolerant wide fan-in dynamic OR gate with two new keeper designs is proposed which are capable of reducing the contention between the keeper and PDN and hence capable of reducing the power dissipation and delay.

Seller Inventory # 9783659648946

Bibliographic Details

• Title: Process Variation Tolerant VLSI Designs : Highly Robust and Process Variation Tolerant CMOS Dynamic Logic Designs
• Publisher: LAP LAMBERT Academic Publishing
• Publication Date: 2014
• Language: English
• ISBN 10: 3659648949
• ISBN 13: 9783659648946
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 220W x 150H x 5D millimeters 220 millimeters width by 150 millimeters height by 5 millimeters depth
• Weight: 137 grams

About this title

Synopsis

Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise margin compared to that of standard CMOS gates. Traditionally, this issue has been resolved by employing a pMOS keeper circuit that compensates for leakage current of the pull-down nMOS network. In the earlier technology nodes, the keeper circuit could improve reliability of the dynamic gates with minor performance penalty. However, aggressive scaling trends of CMOS technology along with increasing levels of process variations have reduced effectiveness of the traditional keeper approach. This problem is more severe in wide fan-in dynamic gates due to the large number of leaky nMOS devices connected to the dynamic node. In this work a process variation tolerant wide fan-in dynamic OR gate with two new keeper designs is proposed which are capable of reducing the contention between the keeper and PDN and hence capable of reducing the power dissipation and delay.