Process Variation Tolerant VLSI Designs : Highly Robust and Process Variation Tolerant CMOS Dynamic Logic Designs

Language: English

Published by LAP LAMBERT Academic Publishing, 2014

3659648949 / 9783659648946

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nach der Bestellung gedruckt Neuware - Printed after ordering - Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise margin compared to that of standard CMOS gates. Traditionally, this issue has been resolved by employing a pMOS keeper circuit that compensates for leakage current of the pull-down nMOS network. In the earlier technology nodes, the keeper circuit could improve reliability of the dynamic gates with minor performance penalty. However, aggressive scaling trends of CMOS technology along with increasing levels of process variations have reduced effectiveness of the traditional keeper approach. This problem is more severe in wide fan-in dynamic gates due to the large number of leaky nMOS devices connected to the dynamic node. In this work a process variation tolerant wide fan-in dynamic OR gate with two new keeper designs is proposed which are capable of reducing the contention between the keeper and PDN and hence capable of reducing the power dissipation and delay.…

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Title
Process Variation Tolerant VLSI Designs : Highly Robust and Process Variation Tolerant CMOS Dynamic Logic Designs
Author
Vikas Mahor
Publisher
LAP LAMBERT Academic Publishing
Publication year
2014
Condition
Neu
Binding
Taschenbuch
Language
English
ISBN 10
3659648949
ISBN 13
9783659648946
Item weight
137 grams
Dimensions
220x150x6 mm

AHA-BUCH GmbH

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