Vikas Mahor (55 results)

Paperback or Softback. Condition: New. Conceptions VLSI tol�rantes aux variations de processus. Book.

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Taschenbuch. Condition: Neu. Process Variation Tolerant VLSI Designs | Highly Robust and Process Variation Tolerant CMOS Dynamic Logic Designs | Vikas Mahor | Taschenbuch | 80 S. | Englisch | 2015 | LAP LAMBERT Academic Publishing | EAN 9783659648946 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu.…

Paperback or Softback. Condition: New. Projetos VLSI tolerantes a varia��es de processo. Book.

Paperback or Softback. Condition: New. Progetti VLSI tolleranti alle variazioni di processo. Book.

Paperback or Softback. Condition: New. Prozessvariationstolerante VLSI-Entw�rfe. Book.

Paperback or Softback. Condition: New. Projekty uklad�w VLSI odporne na wahania procesowe. Book.

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Taschenbuch. Condition: Neu. Projetos VLSI tolerantes a variações de processo | Projetos de lógica dinâmica CMOS altamente robustos e tolerantes a variações de processo | Vikas Mahor | Taschenbuch | Portugiesisch | 2026 | Edições Nosso Conhecimento | EAN 9786209978098 | Verantwortliche Person für die EU: SIA OmniScriptum Publishing, Brivibas Gatve 197, 1039 RIGA, LETTLAND, customerservice[at]vdm-vsg[dot]de | Anbieter: preigu.…

Taschenbuch. Condition: Neu. Prozessvariationstolerante VLSI-Entwürfe | Äußerst robuste und prozessvariationstolerante CMOS-Entwürfe für dynamische Logik | Vikas Mahor | Taschenbuch | 68 S. | Deutsch | 2026 | Verlag Unser Wissen | EAN 9786209962738 | Verantwortliche Person für die EU: SIA OmniScriptum Publishing, Brivibas Gatve 197, 1039 RIGA, LETTLAND, customerservice[at]vdm-vsg[dot]de | Anbieter: preigu.…

Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise margin compared to that of standard CMOS gates. Traditionally, this issue has been resolved by employing a pMOS keeper circuit that compensates for leakage current of the pull-down nMOS network. In the earlier technology nodes, the keeper circuit could improve reliability of the dynamic gates with minor performance penalty. However, aggressive scaling trends of CMOS technology along with increasing levels of process variations have reduced effectiveness of the traditional keeper approach. This problem is more severe in wide fan-in dynamic gates due to the large number of leaky nMOS devices connected to the dynamic node. In this work a process variation tolerant wide fan-in dynamic OR gate with two new keeper designs is proposed which are capable of reducing the contention between the keeper and PDN and hence capable of reducing the power dissipation and delay. 80 pp. Englisch.…

PAP. Condition: New. New Book. Shipped from UK. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000.

Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise margin compared to that of standard CMOS gates. Traditionally, this issue has been resolved by employing a pMOS keeper circuit that compensates for leakage current of the pull-down nMOS network. In the earlier technology nodes, the keeper circuit could improve reliability of the dynamic gates with minor performance penalty. However, aggressive scaling trends of CMOS technology along with increasing levels of process variations have reduced effectiveness of the traditional keeper approach. This problem is more severe in wide fan-in dynamic gates due to the large number of leaky nMOS devices connected to the dynamic node. In this work a process variation tolerant wide fan-in dynamic OR gate with two new keeper designs is proposed which are capable of reducing the contention between the keeper and PDN and hence capable of reducing the power dissipation and delay.…

PAP. Condition: New. New Book. Delivered from our UK warehouse in 4 to 14 business days. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000.

Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Mahor VikasVikas Mahor, received the B.Tech. degree in electronics engineering from the Rajeev Gandhi Technical University, Bhopal, in 2007. In July 2012, he has been awarded with an M. Tech. degree in VLSI Design from Indian Institu.…

Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware 68 pp. Spanisch.

Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise margin compared to that of standard CMOS gates. Traditionally, this issue has been resolved by employing a pMOS keeper circuit that compensates for leakage current of the pull-down nMOS network. In the earlier technology nodes, the keeper circuit could improve reliability of the dynamic gates with minor performance penalty. However, aggressive scaling trends of CMOS technology along with increasing levels of process variations have reduced effectiveness of the traditional keeper approach. This problem is more severe in wide fan-in dynamic gates due to the large number of leaky nMOS devices connected to the dynamic node. In this work a process variation tolerant wide fan-in dynamic OR gate with two new keeper designs is proposed which are capable of reducing the contention between the keeper and PDN and hence capable of reducing the power dissipation and delay.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 80 pp. Englisch.…

PAP. Condition: New. New Book. Shipped from UK. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000.

PAP. Condition: New. New Book. Shipped from UK. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000.

PAP. Condition: New. New Book. Shipped from UK. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000.

PAP. Condition: New. New Book. Shipped from UK. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000.

Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware 68 pp. Französisch.

Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Las puertas dinámicas han resultado ser una excelente opción en el diseño de módulos de alto rendimiento para los microprocesadores modernos. La única limitación de las puertas dinámicas es su margen de ruido relativamente bajo en comparación con el de las puertas CMOS estándar. Tradicionalmente, este problema se ha resuelto empleando un circuito de retención pMOS que compensa la corriente de fuga de la red nMOS de bajada. En los nodos tecnológicos anteriores, el circuito de retención podía mejorar la fiabilidad de las puertas dinámicas con una penalización mínima en el rendimiento. Sin embargo, las tendencias de escalado agresivo de la tecnología CMOS, junto con los crecientes niveles de variaciones de proceso, han reducido la eficacia del enfoque tradicional de retención. Este problema es más grave en las puertas dinámicas de amplia entrada debido al gran número de dispositivos nMOS con fugas conectados al nodo dinámico. En este trabajo se propone una puerta OR dinámica de amplia entrada tolerante a las variaciones de proceso con dos nuevos diseños de circuito de retención, capaces de reducir la contienda entre el circuito de retención y la red de disipación de potencia (PDN) y, por lo tanto, de reducir la disipación de potencia y el retardo.…