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This book presents a study and analysis to investigate of a secret-key sharing in quantum technique and try to increase the key length and security level in the sifting key stage. Enhancements in sifting key stage and error correction stage are done by repeating the QKD protocol and encoding the key bits before sending them by adding a C_QUBITS technique. After that, 60% base probability is used to increase the protocol gain. The prototype is implemented with the default FPGA clock period which is 20 ns; the performance analysis shows a good enhancement in the speed of generation which is less than 20 ns and the number of used hardware pins is just 3 pins.
Title: Quantum Key Distribution Using FPGA: A Real ...
Publisher: Noor Publishing
Publication Date: 2021
Binding: Soft cover
Condition: New
Seller: Lucky's Textbooks, Dallas, TX, U.S.A.
Condition: New. Seller Inventory # ABLIING23Apr0316110299222
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Seller: Chiron Media, Wallingford, United Kingdom
PF. Condition: New. Seller Inventory # 6666-IUK-9786204720067
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Seller: moluna, Greven, Germany
Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Jumaa Noor KareemNoor Kareem Jumaa was received her B.Sc degree in computer engineering from university of Baghdad, Iraq in 2010 and the M.Sc degree in quantum cryptography and data security from the department of electronics and com. Seller Inventory # 548987925
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Seller: Ria Christie Collections, Uxbridge, United Kingdom
Condition: New. In. Seller Inventory # ria9786204720067_new
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Seller: buchversandmimpf2000, Emtmannsberg, BAYE, Germany
Taschenbuch. Condition: Neu. Neuware -This book presents a study and analysis to investigate of a secret-key sharing in quantum technique and try to increase the key length and security level in the sifting key stage. Enhancements in sifting key stage and error correction stage are done by repeating the QKD protocol and encoding the key bits before sending them by adding a C_QUBITS technique. After that, 60% base probability is used to increase the protocol gain. The prototype is implemented with the default FPGA clock period which is 20 ns; the performance analysis shows a good enhancement in the speed of generation which is less than 20 ns and the number of used hardware pins is just 3 pins.Books on Demand GmbH, Überseering 33, 22297 Hamburg 100 pp. Englisch. Seller Inventory # 9786204720067
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Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germany
Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book presents a study and analysis to investigate of a secret-key sharing in quantum technique and try to increase the key length and security level in the sifting key stage. Enhancements in sifting key stage and error correction stage are done by repeating the QKD protocol and encoding the key bits before sending them by adding a C_QUBITS technique. After that, 60% base probability is used to increase the protocol gain. The prototype is implemented with the default FPGA clock period which is 20 ns; the performance analysis shows a good enhancement in the speed of generation which is less than 20 ns and the number of used hardware pins is just 3 pins. 100 pp. Englisch. Seller Inventory # 9786204720067
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Seller: BargainBookStores, Grand Rapids, MI, U.S.A.
Paperback or Softback. Condition: New. Quantum Key Distribution Using FPGA: A Real Time Prototype, Design, and Analysis 0.35. Book. Seller Inventory # BBS-9786204720067
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Seller: California Books, Miami, FL, U.S.A.
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Seller: AHA-BUCH GmbH, Einbeck, Germany
Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - This book presents a study and analysis to investigate of a secret-key sharing in quantum technique and try to increase the key length and security level in the sifting key stage. Enhancements in sifting key stage and error correction stage are done by repeating the QKD protocol and encoding the key bits before sending them by adding a C_QUBITS technique. After that, 60% base probability is used to increase the protocol gain. The prototype is implemented with the default FPGA clock period which is 20 ns; the performance analysis shows a good enhancement in the speed of generation which is less than 20 ns and the number of used hardware pins is just 3 pins. Seller Inventory # 9786204720067
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Seller: PBShop.store UK, Fairford, GLOS, United Kingdom
PAP. Condition: New. New Book. Delivered from our UK warehouse in 4 to 14 business days. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000. Seller Inventory # L0-9786204720067
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