Real Chip Design and Verification Using Verilog and VHDL

Senior Editor and Contributor Ben Cohen

ISBN 10: 1539769712 / ISBN 13: 9781539769712

Published by Createspace Independent Publishing Platform, 2002

About this Item

This item is printed on demand. New copy - Usually dispatched within 5-9 working days 980.

Seller Inventory # C9781539769712

Bibliographic Details

• Title: Real Chip Design and Verification Using Verilog and VHDL
• Publisher: Createspace Independent Publishing Platform
• Publication Date: 2002
• Language: English
• ISBN 10: 1539769712
• ISBN 13: 9781539769712
• Binding: Paperback / softback
• Condition: New

About this title

Synopsis

Real Chip Design and Verification Using Verilog and VHDL addresses the practical and real aspects of logic design, processes, and verification. It incorporates a collection of FPGA and ASIC design practices, and uses Verilog and VHDL as a tool for expression of the desired architectures. This book is not intended to teach either HDL, as there are several books specifically geared toward teaching the languages. However, it provides various architectural design primitives, applications, and verification techniques, along with design methodologies and common practices.

About the Author

Ben Cohen authored the following books:

VHDL Coding Styles and Methodologies,
first and second editions,
VHDL Answers to Frequently Asked Questions, first and second editions
Component Design by Example
... a Step-by-Step Process Using VHDL with UART as Vehicle