Real Chip Design and Verification Using Verilog and VHDL

Cohen, Ben

ISBN 10: 0970539428 / ISBN 13: 9780970539427

Published by VhdlCohen, 2016

About this Item

Connecting readers with great books since 1972! Used textbooks may not include companion materials such as access codes, etc. May have some wear or writing/highlighting. We ship orders daily and Customer Service is our top priority!

Seller Inventory # S_261765328

Bibliographic Details

• Title: Real Chip Design and Verification Using Verilog and VHDL
• Publisher: VhdlCohen
• Publication Date: 2016
• Language: English
• ISBN 10: 0970539428
• ISBN 13: 9780970539427
• Binding: Paperback
• Condition: Good

About this title

Synopsis

This book addresses the practical and real aspects of logic design, processes, and verification. It incorporates a collection of FPGA and ASIC design practices expressed with Verilog and VHDL. Topics: 1. Architectural decomposition process; 2. Fundamental elements including synchronous edge detector, counter styles (e.g., Binary, One-Hot, Gray, Johnson), memories (ROM. RAM, FIFO), EDAC, cell primitives and impact on architecture, clocking schemes and PLL; 3. Asynchronous world, metastability, asynchronous FIFO, crossing clock domains; 4. Transaction-based verification methodology, forcing errors, counter and EDAC verification models; 5. Control machines and implementation methodologies with FSM and microprogrammed solutions; 6. Arithmetic machines, HDL Signed and Unsigned types; 7. Mixed mode simulations and synthesis; 8. Minimizing design errors; 9. Verilog/VHDL comparison, Verilog for VHDL users, Verilog coding style guidelines.

About the Author

Ben Cohen authored the following books:

VHDL Coding Styles and Methodologies,
first and second editions,
VHDL Answers to Frequently Asked Questions, first and second editions
Component Design by Example
... a Step-by-Step Process Using VHDL with UART as Vehicle