Source-Synchronous Networks-On-Chip: Circuit and Architectural Interconnect Modeling

Ayan Mandal

ISBN 10: 1461494044 ISBN 13: 9781461494041
Published by Springer-Verlag New York Inc., 2013
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This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.

From the Back Cover: This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.

• Describes novel methods for high-speed network-on-chip (NoC) design;
• Enables readers to understand NoC design from both circuit and architectural levels;
• Provides circuit-level details of the NoC (including clocking, router design), along with a high-speed, resonant clocking style which is used in the NoC;
• Includes architectural simulations of the NoC, demonstrating significantly superior performance over the state-of-the-art.

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Bibliographic Details

Title: Source-Synchronous Networks-On-Chip: Circuit...
Publisher: Springer-Verlag New York Inc.
Publication Date: 2013
Binding: Hardback
Condition: New

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Condition: Hervorragend. Zustand: Hervorragend | Sprache: Englisch | Produktart: Bücher | This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic. Seller Inventory # 24295134/1

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Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Describes novel methods for high-speed network-on-chip (NoC) design Enables readers to understand NoC design from both circuit and architectural levels Provides circuit-level details of the NoC (including clocking, router design), along wit. Seller Inventory # 4199984

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Buch. Condition: Neu. Source-Synchronous Networks-On-Chip | Circuit and Architectural Interconnect Modeling | Ayan Mandal (u. a.) | Buch | xiii | Englisch | 2013 | Springer US | EAN 9781461494041 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu Print on Demand. Seller Inventory # 105592804

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Buch. Condition: Neu. Neuware -This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized.Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 160 pp. Englisch. Seller Inventory # 9781461494041

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Buch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic. 160 pp. Englisch. Seller Inventory # 9781461494041

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Buch. Condition: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic. Seller Inventory # 9781461494041

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