Test Vector Reordering Method for Low Power Testing

Language: English

Published by LAP LAMBERT Academic Publishing Jul 2012, 2012

3659180769 / 9783659180767

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This item is printed on demand - Print on Demand Titel. Neuware -The book investigates test vector reordering algorithm for minimizing the power dissipation during testing of VLSI circuits. Testing plays a key role in design flow and is the major challenging task for design and test engineers. Power dissipation is critical problem during testing phase. The test vectors generated from Automatic Test Pattern Generator used for testing are statistically independent which leads to more power dissipation. The testing power can be reduced by reordering the sequence of test vectors. The reordering algorithm is developed using the graph theory with heuristic concept to find more sub-optimal solutions. Five functional metrics such as Cosine, Hamming, Mahalanobis, Minkowski and Seuclidean are considered for reordering the test vectors. Don't care replacement method is also proposed for reordered test set to reduce further the transitions in the CUT. Both the methods are implemented and simulated in ISCAS85 benchmark circuits to evaluate the transitions and average power. The results show that transitions and average power are reduced considerably for functions other than hamming distance when compared with unordered test set and existing methods.OmniScriptum SRL, Str. Armeneasca 28/1, office 1, 2012 Chisinau 76 pp. Englisch.…

Seller Inventory # 9783659180767

Title
Test Vector Reordering Method for Low Power Testing
Author
K. Gunavathi
Publisher
LAP LAMBERT Academic Publishing Jul 2012
Publication year
2012
Condition
Neu
Binding
Taschenbuch
Language
English
ISBN 10
3659180769
ISBN 13
9783659180767
Item weight
131 grams
Dimensions
220x150x5 mm

buchversandmimpf2000

Emtmannsberg, BAYE, Germany

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