Discover how cutting‑edge interconnection networks shape ultra‑high‑performance multiprocessors.
This book explains the Ultracomputer’s shared memory design and the tradeoffs between buses, crossbars, and omega networks, with a focus on how network choices affect performance, size, and scalability.
The narrative walks through modular packaging concepts, including the famous “button” technology and ES‑Kit modules. It shows how processor, memory, and switch modules interconnect in stacked packages, and it traces how routing, combining, and arithmetic operations are supported in the network switch. Real‑world prototypes from NYU illustrate how these ideas come to life in practice, from small two‑processor designs to large 256‑ and 4096‑processor configurations.
- Compare different interconnect options (bus, crossbar, omega) and learn their impact on wiring and latency.
- See how 2×2 and 4×4 switches, along with horizontal and vertical routers, enable scalable layouts.
- Explore the practical packaging approach using button technology and ES‑Kit modules.
- Understand prototype evolution—from Ultra I to Ultra II and beyond—and the role of Fetch and Add in the memory system.
Ideal for readers of computer architecture and microprocessor interconnect design who want a concrete look at early high‑performance systems and their packaging challenges.