Here is a practical and useful guide to VHDL synthesis. The purpose of this book is to explain the transformations that occur during the synthesis process from a VHDL model to a netlist. Constructs that are supported for synthesis are clearly explained with many examples with their synthesized netlists.

About the Author:

J. Bhasker, a Distinguished Member of Technical Staff at AT&T Bell Laboratories, has published three other very popular books on VHDL, including a study guide. He has been involved with synthesis for more than ten years and he is one of the main architects of the ArchSyn synthesis system. He has published over twenty papers in journals and conferences and has coached a number of AT&T colleagues through classes on VHDL and synthesis.

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A Vhdl Synthesis Primer

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