Andrzej Strojwas (41 results)
- Hardcover
Seller: Bay State Book Company, North Smithfield, RI, U.S.A.Bay State Book Company
Contact seller5-star sellerCondition: Used - Fair
US$ 47.98
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Condition: acceptable. The book is complete and readable, with all pages and cover intact. Dust jacket, shrink wrap, or boxed set case may be missing. Pages may have light notes, highlighting, or minor water exposure, but nothing that affects readability. May be an ex-library copy and could include library markings or stickers.
Language: English
Published by Kluwer Academic Publishers, Dordrecht, Holland 1997
- Hardcover
- First Edition
Seller: PsychoBabel & Skoob Books, Didcot, United KingdomPsychoBabel & Skoob Books
Contact seller5-star sellerCondition: Used - Very good
US$ 36.27
US$ 16.46 shippingShips from United Kingdom to U.S.A.Quantity: 1 available
hardcover. Condition: Very Good. No Dust Jacket. First Edition. Hardback in very good condition. Printed boards, a little scuffed; previous owner's name on FEP, no jacket as issued; contents clean, sound, bright. TPW. Used.
VLSI Design for Manufacturing: Yield Enhancement
Director, Stephen W., with Wojciech Maly and Andrzej J. Strojwas
- Hardcover
Seller: BookDepart, Shepherdstown, WV, U.S.A.BookDepart
Contact seller5-star sellerCondition: Used - Very good
US$ 65.15
US$ 8.44 shippingShips within U.S.A.Quantity: 1 available
Hardcover. Condition: Very Good. Hardcover; fading and light shelf wear to exterior; light fading to page edges; otherwise in very good condition with clean text, firm binding.
VLSI Design for Manufacturing: Yield Enhancement (The Springer International Series in Engineering and Computer Science)
Director, Stephen W. W.; Maly, Wojciech; Strojwas, Andrzej J.
- Softcover
Seller: Goodwill of Silicon Valley, SAN JOSE, CA, U.S.A.Goodwill of Silicon Valley
Contact seller5-star sellerCondition: Used - Good
US$ 107.34
US$ 3.99 shippingShips within U.S.A.Quantity: 1 available
Condition: good. Supports Goodwill of Silicon Valley job training programs. The cover and pages are in Good condition! Any other included accessories are also in Good condition showing use. Use can include some highlighting and writing, page and cover creases as well as other types visible wear.
- Hardcover
Seller: GreatBookPrices, Columbia, MD, U.S.A.GreatBookPrices
Contact seller5-star sellerCondition: New
US$ 127.56
US$ 2.64 shippingShips within U.S.A.Quantity: Over 20 available
Condition: New.
- Hardcover
Seller: BennettBooksLtd, Los Angeles, CA, U.S.A.BennettBooksLtd
Contact seller5-star sellerCondition: New
US$ 123.26
US$ 6.95 shippingShips within U.S.A.Quantity: 1 available
hardcover. Condition: New. In shrink wrap. Looks like an interesting title.
- Hardcover
Seller: Ria Christie Collections, Uxbridge, United KingdomRia Christie Collections
Contact seller5-star sellerCondition: New
US$ 131.37
US$ 15.77 shippingShips from United Kingdom to U.S.A.Quantity: Over 20 available
Condition: New. In.
- Softcover
Seller: Ria Christie Collections, Uxbridge, United KingdomRia Christie Collections
Contact seller5-star sellerCondition: New
US$ 131.37
US$ 15.77 shippingShips from United Kingdom to U.S.A.Quantity: Over 20 available
Condition: New. In.
- Hardcover
Seller: GreatBookPricesUK, Woodford Green, United KingdomGreatBookPricesUK
Contact seller5-star sellerCondition: New
US$ 131.36
US$ 19.75 shippingShips from United Kingdom to U.S.A.Quantity: Over 20 available
Condition: New.
- Hardcover
Seller: Buchpark, Trebbin, GermanyBuchpark
Contact seller5-star sellerCondition: Used - Very good
US$ 41.66
US$ 119.22 shippingShips from Germany to U.S.A.Quantity: 1 available
Condition: Gut. Zustand: Gut | Sprache: Englisch | Produktart: Bücher | Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Research in (pre-…fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.
- Hardcover
Seller: Kennys Bookshop and Art Galleries Ltd., Galway, GY, IrelandKennys Bookshop and Art Galleries Ltd.
Contact seller5-star sellerCondition: New
US$ 155.07
US$ 11.92 shippingShips from Ireland to U.S.A.Quantity: 15 available
Condition: New. This text applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. Num Pages: 155 pages, b…iography. BIC Classification: TJFC. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly; (UU) Undergraduate. Dimension: 234 x 156 x 11. Weight in Grams: 426. . 1997. Hardback. . . . .
- Hardcover
Seller: Books Puddle, New York, NY, U.S.A.Books Puddle
Contact seller4-star sellerCondition: New
US$ 162.84
US$ 3.99 shippingShips within U.S.A.Quantity: 4 available
Condition: New. pp. 176.
- Hardcover
Seller: GreatBookPricesUK, Woodford Green, United KingdomGreatBookPricesUK
Contact seller5-star sellerCondition: Used - As new
US$ 158.63
US$ 19.75 shippingShips from United Kingdom to U.S.A.Quantity: Over 20 available
Condition: As New. Unread book in perfect condition.
- Hardcover
Seller: Mispah books, Redhill, SURRE, United KingdomMispah books
Contact seller4-star sellerCondition: Used - As new
US$ 147.80
US$ 32.91 shippingShips from United Kingdom to U.S.A.Quantity: 1 available
Hardcover. Condition: Like New. Like NewLIKE NEW. book.
- Hardcover
Seller: GreatBookPrices, Columbia, MD, U.S.A.GreatBookPrices
Contact seller5-star sellerCondition: Used - As new
US$ 178.55
US$ 2.64 shippingShips within U.S.A.Quantity: Over 20 available
Condition: As New. Unread book in perfect condition.
- Hardcover
Seller: Kennys Bookstore, Olney, MD, U.S.A.Kennys Bookstore
Contact seller5-star sellerCondition: New
US$ 186.14
US$ 10.50 shippingShips within U.S.A.Quantity: 15 available
Condition: New. This text applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. Num Pages: 155 pages, b…iography. BIC Classification: TJFC. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly; (UU) Undergraduate. Dimension: 234 x 156 x 11. Weight in Grams: 426. . 1997. Hardback. . . . . Books ship from the US and Ireland.
- Hardcover
Seller: Ria Christie Collections, Uxbridge, United KingdomRia Christie Collections
Contact seller5-star sellerCondition: New
US$ 186.91
US$ 15.77 shippingShips from United Kingdom to U.S.A.Quantity: Over 20 available
Condition: New. In.
VLSI Design for Manufacturing: Yield Enhancement (The Springer International Series in Engineering and Computer Science)
Director, Stephen W. W.; Maly, Wojciech; Strojwas, Andrzej J.
- Softcover
Seller: Ria Christie Collections, Uxbridge, United KingdomRia Christie Collections
Contact seller5-star sellerCondition: New
US$ 186.91
US$ 15.77 shippingShips from United Kingdom to U.S.A.Quantity: Over 20 available
Condition: New. In.
- Hardcover
Seller: AHA-BUCH GmbH, Einbeck, GermanyAHA-BUCH GmbH
Contact seller5-star sellerCondition: New
US$ 131.88
US$ 70.60 shippingShips from Germany to U.S.A.Quantity: 1 available
Buch. Condition: Neu. Druck auf Anfrage Neuware - Printed after ordering - Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Research in (p…re-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.
- Softcover
Seller: Buchpark, Trebbin, GermanyBuchpark
Contact seller5-star sellerCondition: Used - Fine
US$ 94.94
US$ 119.22 shippingShips from Germany to U.S.A.Quantity: 1 available
Condition: Sehr gut. Zustand: Sehr gut | Sprache: Englisch | Produktart: Bücher | Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Researc…h in (pre-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.
- Softcover
Seller: Mispah books, Redhill, SURRE, United KingdomMispah books
Contact seller4-star sellerCondition: Used - As new
US$ 210.17
US$ 32.91 shippingShips from United Kingdom to U.S.A.Quantity: 1 available
Paperback. Condition: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.
- Hardcover
Seller: Books Puddle, New York, NY, U.S.A.Books Puddle
Contact seller4-star sellerCondition: New
US$ 236.60
US$ 3.99 shippingShips within U.S.A.Quantity: 4 available
Condition: New. pp. 308.
- Softcover
Seller: Books Puddle, New York, NY, U.S.A.Books Puddle
Contact seller4-star sellerCondition: New
US$ 239.29
US$ 3.99 shippingShips within U.S.A.Quantity: 4 available
Condition: New. pp. 310.
- Hardcover
Seller: Kennys Bookshop and Art Galleries Ltd., Galway, GY, IrelandKennys Bookshop and Art Galleries Ltd.
Contact seller5-star sellerCondition: New
US$ 235.77
US$ 11.92 shippingShips from Ireland to U.S.A.Quantity: 15 available
Condition: New. Series: The Springer International Series in Engineering and Computer Science. Num Pages: 292 pages, biography. BIC Classification: TJFC. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly. Dimension: 234 x 156 x 19. Weight in Grams: 609. . 1989. Hardback. . . . .
- Hardcover
Seller: moluna, Greven, Germanymoluna
Contact seller5-star sellerCondition: New
US$ 211.04
US$ 55.62 shippingShips from Germany to U.S.A.Quantity: Over 20 available
Gebunden. Condition: New. One of the keys to success in the IC industry is getting a new product to market in a timely fashion and being able to produce that product with sufficient yield to be profitable. There are two ways to increase yield: by improving the control of the manufac.
- Hardcover
Seller: Kennys Bookstore, Olney, MD, U.S.A.Kennys Bookstore
Contact seller5-star sellerCondition: New
US$ 283.72
US$ 10.50 shippingShips within U.S.A.Quantity: 15 available
Condition: New. Series: The Springer International Series in Engineering and Computer Science. Num Pages: 292 pages, biography. BIC Classification: TJFC. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly. Dimension: 234 x 156 x 19. Weight in Grams: 609. . 1989. Hardback. . . . . Books ship from the… US and Ireland.
- Hardcover
Seller: Mispah books, Redhill, SURRE, United KingdomMispah books
Contact seller4-star sellerCondition: Used - As new
US$ 348.48
US$ 32.91 shippingShips from United Kingdom to U.S.A.Quantity: 1 available
Hardcover. Condition: Like New. Like New. book.
- Hardcover
Seller: Celler Versandantiquariat, Eicklingen, GermanyCeller Versandantiquariat
Contact seller5-star sellerAssociation member: GIAQ
Condition: Used
US$ 30.41
US$ 43.15 shippingShips from Germany to U.S.A.Quantity: 1 available
Kluwer, Boston, 1990. XII, 291 pages with some graphics, hardcover, (former library book)--- 750 Gramm.
- Softcover
- Print on Demand
Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermanyBuchWeltWeit Ludwig Meier e.K.
Contact seller5-star sellerCondition: New
US$ 125.12
US$ 26.11 shippingShips from Germany to U.S.A.Quantity: 2 available
Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabr…ication. Research in (pre-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing. 176 pp. Englisch.
- Softcover
- Print on Demand
Seller: moluna, Greven, Germanymoluna
Contact seller5-star sellerCondition: New
US$ 107.91
US$ 55.62 shippingShips from Germany to U.S.A.Quantity: Over 20 available
Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before… and after fabrication. Research in .
