David Overhauser (38 results)
- Softcover
Seller: ThriftBooks-Atlanta, AUSTELL, U.S.A.ThriftBooks-Atlanta
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Paperback. Condition: As New. No Jacket. Pages are clean and are not marred by notes or folds of any kind. ~ ThriftBooks: Read More, Spend Less.
- Softcover
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- Softcover
Seller: California Books, Miami, U.S.A.California Books
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- Softcover
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Condition: As New. Unread book in perfect condition.
Language: English
Published by Kluwer Academic Publishers, Norwell, Massachusetts, U.S.A. 1995
- Hardcover
- First Edition
Seller: PsychoBabel & Skoob Books, Didcot, United KingdomPsychoBabel & Skoob Books
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US$ 21.15
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hardcover. Condition: Very Good. No Dust Jacket. First Edition. White hardcover with white lettering on spine and upper board and contents in very good clean condition, showing minimal signs of wear. Previous owner's name on FEP. Profusely illustrated by diagrams and tables. No dust jacket. T. Used.
Switch-Level Timing Simulation of MOS VLSI Circuits (The Kluwer International Series in Engineering and Computer Science; 66. VLSI, Computer Architecture and Digital Signal Processing)
Rao, Vasant; Overhauser, David; Trick, Timothy; Hajj, Ibrahim
Language: English
Published by Kluwer Academic Publishers, Norwell, Massachusetts, U.S.A. 1989
- Hardcover
- First Edition
Seller: PsychoBabel & Skoob Books, Didcot, United KingdomPsychoBabel & Skoob Books
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US$ 38.75
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hardcover. Condition: Very Good. No Dust Jacket. First Edition. White hardcover with black lettering on spine and upper board and contents in very good clean condition, showing minimal signs of wear. Previous owner's name on FEP. Profusely illustrated by diagrams and tables. No dust jacket. T. Used.
- Softcover
Seller: GreatBookPricesUK, Woodford Green, United KingdomGreatBookPricesUK
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Published by Kluwer Academic Publishers 1995 1995
Seller: Wonderland Books, Berkeley, U.S.A.Wonderland Books
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- Softcover
Seller: GreatBookPricesUK, Woodford Green, United KingdomGreatBookPricesUK
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US$ 39.97
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Condition: As New. Unread book in perfect condition.
- Softcover
Seller: moluna, Greven, Germanymoluna
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US$ 35.84
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Condition: New. Über den AutorDavid Overhauser, Ph.D., began working with startups in 1980. He has been involved in over 20 startups in a variety of roles over 35 years, including engineer, Vice President, Founder, Board Member, investor, co.
Switch-Level Timing Simulation of MOS VLSI Circuits (The Springer International Series in Engineering and Computer Science, 66)
Rao, Vasant B.; Overhauser, David V.; Trick, Timothy N.; Hajj, Ibrahim N.
- Softcover
Seller: Ria Christie Collections, Uxbridge, United KingdomRia Christie Collections
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Switch-Level Timing Simulation of MOS VLSI Circuits (The Springer International Series in Engineering and Computer Science, 66)
Rao, Vasant B.; Overhauser, David V.; Trick, Timothy N.; Hajj, Ibrahim N.
- Hardcover
Seller: Ria Christie Collections, Uxbridge, United KingdomRia Christie Collections
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Condition: New. In.
- Hardcover
Seller: Buchpark, Trebbin, GermanyBuchpark
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Condition: Gut. Zustand: Gut | Seiten: 292 | Sprache: Englisch | Produktart: Bücher | Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-tim…ing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques.
- Hardcover
Seller: Books Puddle, New York, U.S.A.Books Puddle
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Condition: New. pp. 224.
- Softcover
Seller: Books Puddle, New York, U.S.A.Books Puddle
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Condition: New. pp. 224.
Switch-Level Timing Simulation of MOS VLSI Circuits
Vasant B. Rao|David V. Overhauser|Timothy N. Trick|Ibrahim N. Hajj
- Hardcover
Seller: moluna, Greven, Germanymoluna
Contact seller5-star sellerCondition: New
US$ 141.87
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Condition: New. Only two decades ago most electronic circuits were designed with a slide-rule, and the designs were verified using breadboard techniques. Simulation tools were a research curiosity and in general were mistrusted by most designers and test engineers. In thos.
- Softcover
Seller: Ria Christie Collections, Uxbridge, United KingdomRia Christie Collections
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US$ 190.64
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Condition: New. In.
- Hardcover
Seller: Ria Christie Collections, Uxbridge, United KingdomRia Christie Collections
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Condition: New. In.
Switch-Level Timing Simulation of MOS VLSI Circuits
Vasant B. Rao|David V. Overhauser|Timothy N. Trick|Ibrahim N. Hajj
- Softcover
Seller: moluna, Greven, Germanymoluna
Contact seller5-star sellerCondition: New
US$ 152.57
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Condition: New. Only two decades ago most electronic circuits were designed with a slide-rule, and the designs were verified using breadboard techniques. Simulation tools were a research curiosity and in general were mistrusted by most designers and test engineers. In thos.
- Softcover
Seller: Books Puddle, New York, U.S.A.Books Puddle
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US$ 235.08
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Condition: New. pp. 294 Index.
- Hardcover
Seller: Books Puddle, New York, U.S.A.Books Puddle
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US$ 236.93
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Condition: New. pp. 292 Index.
Switch-Level Timing Simulation of MOS VLSI Circuits (The Springer International Series in Engineering and Computer Science, 66)
Rao, Vasant B., Overhauser, David V., Trick, Timothy N., Haj
- Hardcover
Seller: Mispah books, Redhill, United KingdomMispah books
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US$ 214.37
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Hardcover. Condition: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.
Switch-Level Timing Simulation of MOS VLSI Circuits (The Springer International Series in Engineering and Computer Science (66))
Rao, Vasant B., Overhauser, David V., Trick, Timothy N., Haj
- Softcover
Seller: Mispah books, Redhill, United KingdomMispah books
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US$ 214.37
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Paperback. Condition: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.
- Softcover
Seller: AHA-BUCH GmbH, Einbeck, GermanyAHA-BUCH GmbH
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US$ 199.86
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Taschenbuch. Condition: Neu. Druck auf Anfrage Neuware - Printed after ordering - Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing,… switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques.
- Softcover
Seller: Mispah books, Redhill, United KingdomMispah books
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US$ 272.45
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Paperback. Condition: Like New. Like New. book.
- Hardcover
Seller: Mispah books, Redhill, United KingdomMispah books
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- Hardcover
- Print on Demand
Seller: Majestic Books, Hounslow, United KingdomMajestic Books
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Condition: New. Print on Demand pp. 224 52:B&W 6.14 x 9.21in or 234 x 156mm (Royal 8vo) Case Laminate on White w/Gloss Lam.
- Softcover
- Print on Demand
Seller: Majestic Books, Hounslow, United KingdomMajestic Books
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US$ 166.21
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Condition: New. Print on Demand pp. 224 49:B&W 6.14 x 9.21 in or 234 x 156 mm (Royal 8vo) Perfect Bound on White w/Gloss Lam.
- Hardcover
- Print on Demand
Seller: Biblios, frankfurt am main, GermanyBiblios
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US$ 175.57
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Condition: New. PRINT ON DEMAND pp. 224.
- Softcover
- Print on Demand
Seller: Biblios, frankfurt am main, GermanyBiblios
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Condition: New. PRINT ON DEMAND pp. 224.
