Kumar Jiwesh (14 results)
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Paperback or Softback. Condition: New. FPGA Implementation of MPEG-2 Video decoder. Book.
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- Softcover
- Print on Demand
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PAP. Condition: New. New Book. Shipped from UK. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000.
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- Print on Demand
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PAP. Condition: New. New Book. Delivered from our UK warehouse in 4 to 14 business days. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000.
- Softcover
- Print on Demand
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Kartoniert / Broschiert. Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Kumar JiweshJiwesh Kumar, B.Tech Electronics and Communication Engineering, NIT Bhopal, Systems Engineer at BrahMos AerospaceAutor/Autorin: Pandey PranjalJiwesh Kumar, B.Tech El…ectronics and Communication Engineering, NI.
FPGA Implementation of MPEG-2 Video decoder : FPGA Implementation of base layer MPEG-2 Video decoder
- Softcover
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Seller: AHA-BUCH GmbH, Einbeck, GermanyAHA-BUCH GmbH
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Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - The MPEG-2 video bitstream without any Scalable Modes is called the Base layer bitstream. The work involves designing the MPEG-2 video decoder and related interfacing logic for reading the MPEG file from flash memory, storing the decoded… data in SDRAM and displaying the video on the SVGA monitor by reading the data from SRAM. We have used the C code as the reference, provided by the MPEG Software Simulation Groups. The bit-by-bit algorithm, for decoding the base layer Mpeg-2 video stream, was abstracted from the C code and the corresponding hardware module for decoding the sequence was designed in VHDL using Quartus 6.2 tool supplied by Altera. The designed decoder module takes the serial bit stream in MPEG-2 format from Flash Memory as input, parses the system layer and decodes the video data. The output is provided in 24 bit RGB form. The MPEG-2 file resides in the flash memory, from where it is read byte-by-byte by the decoder module. The decoded frame is written to the SRAM, which dual ported to act as VIDEO RAM or VRAM. The VGA controller reads continuously from the VRAM and displays the video on monitor. The design was implemented on DE1 university program' board.
