Soares Ag (39 results)
Language: English
Published by Gypsy Press, 2025
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paperback. Condition: Very Good. Connecting readers with great books since 1972! Used books may not include companion materials, and may have some shelf wear or limited writing. We ship orders daily and Customer Service is our top priority.
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Published by Gypsy Press, 2025
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Published by Gypsy Press, 2025
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Published by Gypsy Press, 2025
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Language: English
Published by Gypsy Press, 2026
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Paperback. Condition: Very Good. No Jacket. May have limited writing in cover pages. Pages are unmarked. ~ ThriftBooks: Read More, Spend Less.
Language: English
Published by Gypsy Press, 2026
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Seller: California Books, Miami, FL, U.S.A.California Books
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Language: English
Published by Gypsy Press, 2025
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Language: English
Published by Amazon Digital Services LLC - Kdp, 2025
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PAP. Condition: New. New Book. Shipped from UK. Established seller since 2000.
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Seller: Phatpocket Limited, Waltham Abbey, HERTS, United KingdomPhatpocket Limited
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Condition: Good. Your purchase helps support Sri Lankan Children's Charity 'The Rainbow Centre'. Ex-library, so some stamps and wear, but in good overall condition. Our donations to The Rainbow Centre have helped provide an education and a safe haven to hundreds of children who live in appalling conditions.
mTOR pathway inhibition attenuates skeletal muscle growth induced by stretching., ?.
Aoki, M. S., Miyabara, E. H., Soares, A. G., Saito, E. T., Moriscot, A. S.
Published by Cell Tiss Res. 324, 149-156 (2006),, 2006
- Softcover
Seller: Antiquariat Petri, Jena, GermanyAntiquariat Petri
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Add to basketSC. Condition: Gut. Obr., 7s., in gutem Zustand, [SD216]., Deu 400g.
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- First Edition
Seller: Better World Books, Mishawaka, IN, U.S.A.Better World Books
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Condition: Very Good. 1st Edition. Former library copy. Pages intact with possible writing/highlighting. Binding strong with minor wear. Dust jackets/supplements may not be included. Includes library markings. Stock photo provided. Product includes identifying sticker. Better World Books: Buy Books. Do Good.
Design of Systems on a Chip: Design and Test.
Reis, Ricardo; Lubaszewski, Marcelo; Jess, Jochen A.G. (Eds.)
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Seller: Universitätsbuchhandlung Herta Hold GmbH, Berlin, GermanyUniversitätsbuchhandlung Herta Hold GmbH
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X, 233 p. Hardcover. Versand aus Deutschland / We dispatch from Germany via Air Mail. Einband bestoßen, daher Mängelexemplar gestempelt, sonst sehr guter Zustand. Imperfect copy due to slightly bumped cover, apart from this in very good condition. Stamped. Stamped. Sprache: Englisch.
Language: English
Published by Independently Published Feb 2025, 2025
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Taschenbuch. Condition: Neu. Neuware - What happens when the Cold War ends-but its ghosts refuse to stand down It's 1999. The Soviet Union has fallen, the old world order is collapsing, and the men who built their careers in the shadows of that conflict are still out there-and they aren't ready to retire.Tom Harrington is an Ame…rican college student backpacking across Europe, chasing cheap trains and summer freedom. When a covert intelligence network known as Phoenix becomes convinced he possesses a stolen microchip containing explosive Cold War secrets, his trip turns into a manhunt.Tom has no idea why they're after him.He only knows they're willing to kill for it.Forced into an uneasy alliance with Harry Fletcher-a veteran British operative running an off-the-books intelligence unit-Tom is pulled into a hidden struggle between former spies, rogue assets, and governments desperate to control information that could destabilize Europe's fragile new order.From the Scottish Highlands to Paris, Venice, and the Swiss Alps, The Phoenix Gambit delivers a fast-paced international espionage thriller of betrayal, pursuit, and survival.For readers of Cold War spy novels, conspiracy thrillers, and action-packed European suspense, A. G. Soares's The Phoenix Gambit explores the dangerous vacuum between empires, the intelligence networks that refuse to die, and the moment an ordinary young man is pulled into a world he will never fully escape.
Language: English
Published by Amazon Digital Services LLC - Kdp Feb 2026, 2026
- Softcover
Seller: AHA-BUCH GmbH, Einbeck, GermanyAHA-BUCH GmbH
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Taschenbuch. Condition: Neu. Neuware - When a hostage rescue in Afghanistan collapses, one British agent discovers the war is only the cover story.It's 2002, in the opening years of the Global War on Terror. When an American journalist is taken hostage inside a remote Afghan fortress, Britain and the United States launch a joint… covert mission to bring her home.British agent Tom Harrington-operating under military cover-is assigned to lead the assault into the mountains of northern Afghanistan. The mission is supposed to be precise. Contained. Plausibly deniable.It goes catastrophically wrong.As the operation unravels, Tom uncovers fractures in the intelligence picture: conflicting briefings, buried agendas, and a CIA presence far too invested in the outcome. What begins as a hostage rescue becomes a trail of betrayal leading from Whitehall briefing rooms to forward bases in Afghanistan, Mediterranean ports, shadowed villas, and diplomatic back channels.Someone wants this chaos.And someone is profiting from it.In The Silent Directorate, Tom follows the evidence beyond rogue operatives and battlefield mistakes to a hidden architecture of power: an organization that manufactures instability, manipulates regime change, and operates beyond nations and flags.For readers of John le Carré, Mick Herron, Daniel Silva, and grounded espionage thrillers, A. G. Soares's The Silent Directorate is a psychologically driven spy novel about covert wars, institutional betrayal, and the moral cost of confronting power that was never meant to be seen.The deeper Tom digs, the clearer it becomes: exposing the truth may not save him.It may turn him into the very thing he is hunting.
- Hardcover
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Condition: Sehr gut. Zustand: Sehr gut | Sprache: Englisch | Produktart: Bücher | Design of Systems on a Chip: Design&Test is the second of two volumes addressing the design challenges associated with new generations of the semiconductor technology. The various chapters are the compilations of tutorials presented at workshops in… the recent years by prominent authors from all over the world. Technology, productivity and quality are the main aspects under consideration to establish the major requirements for the design and test of upcoming systems on a chip. In particular this second book include contributions on three different, but complementary axes: core design, computer-aided design tools and test methods. A collection of chapters deal with the heterogeneity aspect of core designs, showing the diversity of parts that may share the same substrate in a state-of-the-art system on a chip. The second part of the book discusses CAD in three different levels of design abstraction, from system level to physical design. The third part deals with test methods. The topic is addressed from different viewpoints: in terms of chip complexity, test is discussed from the core and system prospective; in terms of signal heterogeneity, the digital, mixed-signal and microsystem prospective are considered. Fault-tolerance in integrated circuits is not an exclusive concern regarding space designers or highly-reliable application engineers. Rather, designers of next generation products must cope with reduced margin noises due to technological advances. The continuous evolution of the fabrication technology process of semiconductor components, in terms of transistor geometry shrinking, power supply, speed, and logic density, has significantly reduced the reliability of very deep submicron integrated circuits, in face of the various internal and external sources of noise. The very popular Field Programmable Gate Arrays, customizable by SRAM cells, are a consequence of the integrated circuit evolution with millions of memory cells to implement the logic, embedded memories, routing, and more recently with embedded microprocessors cores. These re-programmable systems-on-chip platforms must be fault-tolerant to cope with present days requirements. This book discusses fault-tolerance techniques for SRAM-based Field Programmable Gate Arrays (FPGAs). It starts by showing the model of the problem and the upset effects in the programmable architecture. In the sequence, it shows the main fault tolerance techniques used nowadays to protect integrated circuits against errors. A large set of methods for designing fault tolerance systems in SRAM-based FPGAs is described. Some presented techniques are based on developing a new fault-tolerant architecture with new robustness FPGA elements. Other techniques are based on protecting the high-level hardware description before the synthesis in the FPGA. The reader has the flexibility of choosing the most suitable fault-tolerance technique for its project and to compare a set of fault toleranttechniques for programmable logic applications.
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Published by Bone Hill, Chiswell Green, St. Albans, Hertfordshire, England : The National Rose Society of Great Britain, 1961., 1961
- Hardcover
Seller: Joseph Valles - Books, Stockbridge, GA, U.S.A.Joseph Valles - Books
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Add to basketHardcover. Condition: Good. 207 pp ; photographs in black & white and in color ; 25 cm. ; green textured cloth with gold lettering and decorations ; several photographs of important hybridizers and rose growers, and several color plates of new roses for 1961, including Super Star, Daily Sketch, Mischief, Stella, Lucy Cramphorn,…Sabrina, Memoriam, Dearest, Fritz Thiedemann, Lilac Cream, Miss Ireland, Orange Sensation and Pink Parfait ; numerous interesting and important articles on rose growing ; Contents : Patrons, Officers And Council -- Arrangements For 1961 -- Report Of The Council -- Balance Sheets -- Presidents And Awards -- The President's Page, By F. Royalton Kisch, M.C., President -- A Great Venture, By F. Fairbrother, M.Sc., F.R.I.C. -- Recent Research On Roses, By E. F. Allen -- The Rose Garden Of Rome, By Stelvio Coggiatti -- The Late Charles Mallerin, By André Leroy, Louis Laperrière And M. Perroud -- Looking At Roses, By Constancewheatcroft -- Rose Arrangements, By Ena Harkness -- Book Review, By F. Fairbrother, M.Sc., F.R.I.C. -- My Grandmother's Roses, By Arbel. M. Aldous -- Rose Culture In The Tropics, By Rev. P. Soares -- The Local Incidence Of Rose Disease, By A. Dick, B.Sc., M.D.,J. Clarke, Lieut.-Col. D. Pope, F. H. Morse -- Lessons From Derriaghy, By Sam McGredy -- Red Roses, By C. Walter Gregory -- The "Floiuade" At Rotterdam 1960, By A. P. C. Dickson -- Common Mistakes In Rose Growing, By R. L. Pallett -- The Yellow Roses, By Bertram Park, O.B.E., V.M.H., Mtrite Agri -- The Unorthodox Rose Grower, By F. C. H. Witchell -- By The Way, By W. J. W. Sanday -- Fifty Years Of The Rose Annual, By A. Norman -- Garden View, By J. H. Wilding -- A Modern Approach To Rose Deterioration And Disease, By Aphra P. Wilson, M.B.E., A.R.C.S. -- "Overhead Watering Prevents Black Spot?" By Roy Hay -- Whose Roses? From A Correspondent Of The Times -- Display Gardens, By Sir Harry Pilkington . -- What's In A Name? By W. C. Thom -- Special Encouragement For Amateur Hybridists, By Edgar M. Allen, C.M.G. -- Highlights In A Veteran Rose Grower's Life, By Edgar M. Allen, C.M.G. -- An Itinerant 'Frau Karl Druschki', By Mrs. F. M. Briscoe -- Roses Which Deserve Greater Recognition, By Rosemary James -- Plant Breeders' Rights, By Gordon Edwards, C.B.E. -- The Spring Competition, By A. J. Huxley -- The Great Summer Rose Show, By A. G. L. Hellyer -- The Artistic Classes, By Julia Clements -- Bristol Group's Annual Show -- Northern Rose Show, By Mr. And Mrs. Joseph C. Watson -- The Great Autumn Rose Show, By Gordon Forsyth -- The Trial Ground, By H. Edland -- Show Awards And Trial Ground Awards 1960 -- International Awards 1960 -- The Rose Analysis, By H. Edland -- Monochrome Plates -- The President -- New Headquarters Of The National Rose Society, Bone Hill, Chiswell Green, St. Albans, Hertfordshire -- Royal Lodge, Windsor -- The Municipal Rose Gardens, Rome -- The Late Charles Mallerin -- The Silver Plate And Spoons -- The Poulsen "Family" -- Alain And Michke Meilland -- "Just Don't Get Him Started Talking About His Roses" -- 'Vanity' -- Colour Plates -- Super Star -- Daily Sketch -- Mischief -- Gold Crown -- Golden Giant -- Stella -- Lucy Cramphorn -- Sabrina -- Memoriam -- Dearest -- Fritz Thiedemann -- Lilac Charm -- Miss Ireland -- Orange Sensation -- Pink Parfait ; no dustjacket ; G. Book.
- Softcover
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Seller: Ria Christie Collections, Uxbridge, United KingdomRia Christie Collections
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- Hardcover
Seller: Books Puddle, New York, NY, U.S.A.Books Puddle
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Condition: New. pp. 244.
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Taschenbuch. Condition: Neu. Design of Systems on a Chip: Design and Test | Ricardo Reis (u. a.) | Taschenbuch | x | Englisch | 2010 | Springer | EAN 9781441940896 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu.
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Buch. Condition: Neu. Druck auf Anfrage Neuware - Printed after ordering - Design of Systems on a Chip: Design&Test is the second of two volumes addressing the design challenges associated with new generations of the semiconductor technology. The various chapters are the compilations of tutorials presented at workshops in the re…cent years by prominent authors from all over the world. Technology, productivity and quality are the main aspects under consideration to establish the major requirements for the design and test of upcoming systems on a chip. In particular this second book include contributions on three different, but complementary axes: core design, computer-aided design tools and test methods. A collection of chapters deal with the heterogeneity aspect of core designs, showing the diversity of parts that may share the same substrate in a state-of-the-art system on a chip. The second part of the book discusses CAD in three different levels of design abstraction, from system level to physical design. The third part deals with test methods. The topic is addressed from different viewpoints: in terms of chip complexity, test is discussed from the core and system prospective; in terms of signal heterogeneity, the digital, mixed-signal and microsystem prospective are considered.Fault-tolerance in integrated circuits is not an exclusive concern regarding space designers or highly-reliable application engineers. Rather, designers of next generation products must cope with reduced margin noises due to technological advances. The continuous evolution of the fabrication technology process of semiconductor components, in terms of transistor geometry shrinking, power supply, speed, and logic density, has significantly reduced the reliability of very deep submicron integrated circuits, in face of the various internal and external sources of noise. The very popular Field Programmable Gate Arrays, customizable by SRAM cells, are a consequence of the integrated circuit evolution with millions of memory cells to implement the logic, embedded memories, routing, and more recently with embedded microprocessors cores. These re-programmable systems-on-chip platforms must be fault-tolerant to cope with present days requirements. This book discusses fault-tolerance techniques for SRAM-based Field Programmable Gate Arrays (FPGAs). It starts by showing the model of the problem and the upset effects in the programmable architecture. In the sequence, it shows the main fault tolerance techniques used nowadays to protect integrated circuits against errors. A large set of methods for designing fault tolerance systems in SRAM-based FPGAs is described. Some presented techniques are based on developing a new fault-tolerant architecture with new robustness FPGA elements. Other techniques are based on protecting the high-level hardware description before the synthesis in the FPGA. The reader has the flexibility of choosing the most suitable fault-tolerance technique for its project and to compare a set of fault toleranttechniques for programmable logic applications.
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- Softcover
Seller: AHA-BUCH GmbH, Einbeck, GermanyAHA-BUCH GmbH
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Taschenbuch. Condition: Neu. Druck auf Anfrage Neuware - Printed after ordering - Design of Systems on a Chip: Design&Test is the second of two volumes addressing the design challenges associated with new generations of the semiconductor technology. The various chapters are the compilations of tutorials presented at workshops in… the recent years by prominent authors from all over the world. Technology, productivity and quality are the main aspects under consideration to establish the major requirements for the design and test of upcoming systems on a chip. In particular this second book include contributions on three different, but complementary axes: core design, computer-aided design tools and test methods. A collection of chapters deal with the heterogeneity aspect of core designs, showing the diversity of parts that may share the same substrate in a state-of-the-art system on a chip. The second part of the book discusses CAD in three different levels of design abstraction, from system level to physical design. The third part deals with test methods. The topic is addressed from different viewpoints: in terms of chip complexity, test is discussed from the core and system prospective; in terms of signal heterogeneity, the digital, mixed-signal and microsystem prospective are considered.Fault-tolerance in integrated circuits is not an exclusive concern regarding space designers or highly-reliable application engineers. Rather, designers of next generation products must cope with reduced margin noises due to technological advances. The continuous evolution of the fabrication technology process of semiconductor components, in terms of transistor geometry shrinking, power supply, speed, and logic density, has significantly reduced the reliability of very deep submicron integrated circuits, in face of the various internal and external sources of noise. The very popular Field Programmable Gate Arrays, customizable by SRAM cells, are a consequence of the integrated circuit evolution with millions of memory cells to implement the logic, embedded memories, routing, and more recently with embedded microprocessors cores. These re-programmable systems-on-chip platforms must be fault-tolerant to cope with present days requirements. This book discusses fault-tolerance techniques for SRAM-based Field Programmable Gate Arrays (FPGAs). It starts by showing the model of the problem and the upset effects in the programmable architecture. In the sequence, it shows the main fault tolerance techniques used nowadays to protect integrated circuits against errors. A large set of methods for designing fault tolerance systems in SRAM-based FPGAs is described. Some presented techniques are based on developing a new fault-tolerant architecture with new robustness FPGA elements. Other techniques are based on protecting the high-level hardware description before the synthesis in the FPGA. The reader has the flexibility of choosing the most suitable fault-tolerance technique for its project and to compare a set of fault toleranttechniques for programmable logic applications.
Design of Systems on a Chip: Design and Test
Reis, Ricardo (Editor) / Soares Lubaszewski, Marcelo (Editor) / Jess, Jochen A.G. (Editor)
- Softcover
Seller: Revaluation Books, Exeter, United KingdomRevaluation Books
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Paperback. Condition: Brand New. 297 pages. 9.00x6.00x0.55 inches. In Stock.
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