Zhan Chenchang (10 results)

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Taschenbuch. Condition: Neu. Output-Capacitor-Free Low-Dropout Regulators: Analysis and Design | Analysis and Design of High-Performance CMOS Output-Capacitor-Free Low-Dropout Regulators for System-on-Chip | Chenchang Zhan (u. a.) | Taschenbuch | 144 S. | Englisch | 2012 | LAP LAMBERT Academic Publishing | EAN 9783659291883 | Verantwortliche Person für die EU: OmniScriptum GmbH & Co. KG, Bahnhofstr. 28, 66111 Saarbrücken, info[at]akademikerverlag[dot]de | Anbieter: preigu.

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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Low-dropout regulators (LDRs) are indispensable components widely used in system-on-chip (SoC) designs to power up noise-sensitive blocks. With the proliferation of portable applications, LDRs are required to have accurate and fast regulation with low quiescent current consumption, compact chip area and without requiring any off-chip capacitors. This research focuses on the analysis and design of high-performance CMOS output-capacitor-free LDRs for SoC power management applications. Three different topologies: adaptively biased LDRs, adaptively biased LDRs with subthreshold undershoot-reduction, and LDRs with low-quiescent current and high power-supply-rejections are analyzed, designed and verified. They are powerful candidates for supplying different blocks of SoC: analog, mixed-signal, digital, and RF. Design-oriented and in-depth theoretical analysis is presented. With these topologies at hand, a cost-effective power management solution for SoC is easier-than-ever to construct. 144 pp. Englisch.

Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Zhan ChenchangDr. Chenchang Zhan is a Senior Engineer at Qualcomm Technologies Inc., San Diego, CA. He is an expert in the analysis and design of analog, mixed-signal and power management IC s which are the subjects he authored or co.

Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Low-dropout regulators (LDRs) are indispensable components widely used in system-on-chip (SoC) designs to power up noise-sensitive blocks. With the proliferation of portable applications, LDRs are required to have accurate and fast regulation with low quiescent current consumption, compact chip area and without requiring any off-chip capacitors. This research focuses on the analysis and design of high-performance CMOS output-capacitor-free LDRs for SoC power management applications. Three different topologies: adaptively biased LDRs, adaptively biased LDRs with subthreshold undershoot-reduction, and LDRs with low-quiescent current and high power-supply-rejections are analyzed, designed and verified. They are powerful candidates for supplying different blocks of SoC: analog, mixed-signal, digital, and RF. Design-oriented and in-depth theoretical analysis is presented. With these topologies at hand, a cost-effective power management solution for SoC is easier-than-ever to construct.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 144 pp. Englisch.

Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Low-dropout regulators (LDRs) are indispensable components widely used in system-on-chip (SoC) designs to power up noise-sensitive blocks. With the proliferation of portable applications, LDRs are required to have accurate and fast regulation with low quiescent current consumption, compact chip area and without requiring any off-chip capacitors. This research focuses on the analysis and design of high-performance CMOS output-capacitor-free LDRs for SoC power management applications. Three different topologies: adaptively biased LDRs, adaptively biased LDRs with subthreshold undershoot-reduction, and LDRs with low-quiescent current and high power-supply-rejections are analyzed, designed and verified. They are powerful candidates for supplying different blocks of SoC: analog, mixed-signal, digital, and RF. Design-oriented and in-depth theoretical analysis is presented. With these topologies at hand, a cost-effective power management solution for SoC is easier-than-ever to construct.