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Add to basketTaschenbuch. Condition: Neu. ASIC Design and Synthesis | RTL Design Using Verilog | Vaibbhav Taraate | Taschenbuch | xxi | Englisch | 2022 | Springer Singapore | EAN 9789813346444 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu.
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Published by Springer Nature Singapore, Springer Nature Singapore, 2022
ISBN 10: 9813346442 ISBN 13: 9789813346444
Language: English
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Add to basketTaschenbuch. Condition: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book describes simple to complex ASIC design practical scenarios using Verilog.Itbuilds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, thecontentsprovide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance.Italso covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.
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Condition: New. 1st ed. 2021 edition NO-PA16APR2015-KAP.
Published by Springer Nature Singapore, Springer Nature Singapore, 2021
ISBN 10: 9813346418 ISBN 13: 9789813346413
Language: English
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Add to basketBuch. Condition: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book describes simple to complex ASIC design practical scenarios using Verilog.Itbuilds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, thecontentsprovide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance.Italso covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.
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