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Processor Array Implementations Mapping by Gusev Marjan (3 results)
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Processor Array Implementations | Mapping Systems of Affine Recurrence Equations for Digital Signal Processing
Language: English
Published by LAP LAMBERT Academic Publishing, 2012
ISBN 10: 3659167592 ISBN 13: 9783659167591
Taschenbuch. Condition: Neu. Processor Array Implementations | Mapping Systems of Affine Recurrence Equations for Digital Signal Processing | Marjan Gusev | Taschenbuch | 288 S. | Englisch | 2012 | LAP LAMBERT Academic Publishing | EAN 9783659167591 | Verantwortliche Person für die EU: BoD - Books on Demand, In de Tarpen 42, 22848 Norderstedt, info[at]bod[dot]de | Anbieter: preigu.
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Processor Array Implementations: Mapping Systems of Affine Recurrence Equations for Digital Signal Processing
Language: English
Published by LAP LAMBERT Academic Publishing, 2012
ISBN 10: 3659167592 ISBN 13: 9783659167591
US$ 190.25
US$ 33.46 shipping
Ships from United Kingdom to U.S.A.Quantity: 1 available
Add to basketPaperback. Condition: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.
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Processor Array Implementations : Mapping Systems of Affine Recurrence Equations for Digital Signal Processing
Language: English
Published by LAP LAMBERT Academic Publishing, 2012
ISBN 10: 3659167592 ISBN 13: 9783659167591
Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Regular processor array implementations lack efficiency due to limitations set by data dependences in order to enable regular data flow. Efficient processor arrays implement data flow of all variables and avoid static variables that require intensive data loads from memory introducing idle processor activity. Most of existing design methods and techniques that map algorithms onto processor arrays are based on linear mappings and just transform the algorithm dependence graphs in space-time graphs. Obtained processor arrays do not reach the required efficiency, producing bubbles when the processor is not performing a reasonable operation in alternative time moments, i.e. producing idle activity. The results in this research show implementations that can eliminate mentioned problems and can reach maximum efficiency, except for processor data load and store activities. The implementations are based on non-linear transformations that include folding, double mapping and fast systolic designs. There are theoretical and experimental proofs which designs can reach the most efficient processor array implementations by introducing the fastest processors array implementations.
