Excerpt from A Cache Technique for Synchronization Variables in Highly Parallel, Shared Memory Systems
Caches have traditionally been used to lower the average latency of memory access. When paired with the individual cpus of a multiprocessor, they have the'additional benefit of reducing the overall load on the processor-memory interconnection. Since synchronization variables have been identified as centers of memory conten tion, we have looked at methods of utilizing the cache to...
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Seller: Forgotten Books, London, United Kingdom
Paperback. Condition: New. Print on Demand. This book explores a technique to minimize network traffic contention which occurs due to synchronization variables acting as the epicenter of memory conflicts. By extending the role of private cache and avoiding the method of identifying commonly targeted variables, the author introduces a new means of reducing network contention. Unlike previous methods that utilize hardware-based directories with global state information for each sharable item, the method outlined in this book draws upon the unique characteristics of banyan network topologies. With a detailed analysis of the advantages and potential drawbacks of this technique, the author presents simulation results that support the feasibility of the proposed methods. The insights provided in this book will be of great interest to researchers and professionals working in the field of parallel computer architecture, particularly those focused on reducing memory contention and optimizing network traffic. This book is a reproduction of an important historical work, digitally reconstructed using state-of-the-art technology to preserve the original format. In rare cases, an imperfection in the original, such as a blemish or missing page, may be replicated in the book. print-on-demand item. Seller Inventory # 9780266784166_0
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