Designing Vlsi Network Nodes to Reduce Memory Traffic in a Shared Memory Parallel Computer - Softcover

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9781333937294: Designing Vlsi Network Nodes to Reduce Memory Traffic in a Shared Memory Parallel Computer

Synopsis

This book delves into the challenges of designing a parallel computer's network nodes. The text positions the detailed study of designing shared memory parallel computers within the broader context of computer engineering and the need to enhance computation speed. The author explores the design of enhanced buffered crossbars and the concept of 'fetch-and-add,' an operation for coordinating tasks in parallel systems. Thematic depth emerges from the insights gained on node design to reduce memory traffic, efficiently manage multiple requests, and prevent serialization. The author also examines architectural features, performance requirements, packaging limitations, and their interplay. The book concludes with a discussion on the significance of combining messages in network nodes, a key technique for improving the overall performance of shared memory parallel computers.

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