CMOS SRAM: CIRCUIT DESIGN AND PARAMETRIC TEST IN NANO-SCALED TECHNOLOGIES (PROCESS-AWARE SRAM DESIGN AND TEST) - Softcover

Pavlov

Softcover

ISBN 10: 8132202325 ISBN 13: 9788132202325

Publisher: Springer India, 2011

Synopsis

As technology scales into nano-meter region, design and test of Static Random Access Memories (SRAMs) becomes a highly complex task. Process disturbances and various defect mechanisms contribute to the increasing number of unstable SRAM cells with parametric sensitivity. Growing sizes of SRAM arrays increase the likelihood of cells with marginal stability and pose strict constraints on transistor parameters distributions. Standard functional tests often fail to detect unstable SRAM cells. Undetected unstable cells deteriorate quality and reliability of the product as such cells may fail to retain the data and cause a system failure. Special design and test measures have to be taken to identify cells with marginal stability. However, it is not sufficient to identify the unstable cells. To ensure reliable system operation, unstable cells have to be repaired. CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and

Edition details

• Publisher: Springer India
• Publication date: 2011
• ISBN 10: 8132202325
• ISBN 13: 9788132202325
• Binding: Paperback
• Language: English
• Edition number: 1