Verilog Styles for Synthesis of Digital Systems
Smith, David R; Franzon, Paul D
Sold by SHIMEDIA, Brooklyn, NY, U.S.A.
AbeBooks Seller since June 30, 2024
New - Soft cover
Condition: New
Ships within U.S.A.
Quantity: 1 available
Add to basketSold by SHIMEDIA, Brooklyn, NY, U.S.A.
AbeBooks Seller since June 30, 2024
Condition: New
Quantity: 1 available
Add to basketSatisfaction Guaranteed or your money back.
Seller Inventory # 0201618605
This book is designed specifically to make the cutting-edge techniques of digital hardware design more accessible to those just entering the field. The text uses a simpler language (Verilog) and standardizes the methodology to the point where even novices can get medium complex designs through to gate-level simulation in a short period of time. Requires a working knowledge of computer organization, Unix, and X windows. Some knowledge of a programming language such as C or Java is desirable, but not necessary. Features a large number of worked examples and problems--from 100 to 100k gate equivalents--all synthesized and successfully verified by simulation at gate level using the VCS compiled simulator, the FPGA Compiler and Behavioral Compiler available from Synopsys, and the FPGA tool suites from Altera and Xilinx. Basic Language Constructs. Structural and Behavioral Specification. Simulation. Procedural Specification. Design Approaches for Single Modules. Validation of Single Modules. Finite State Machine Styles. Control-Point Writing Style. Managing Complexity--Large Designs. Improving Timing, Area, and Power. Design Compiler. Synthesis to Standard Cells. Synthesis to FPGA. Gate Level Simulation and Testing. Alternative Writing Styles. Mixed Technology Design. For anyone wanting an accessible, accelerated introduction to the cutting-edge tools for Digital Hardware Design.
The material available within this book is suitable for professionals who have had an introduction to Boolean algebra and computer organization. A working knowledge of Unix and X-windows is necessary, along with some experience with programming languages such as 'C' or Java. The book uses Verilog and standardizing methodology to such a degree that seniors and first year graduate students can see medium complex designs through the gate level simulation in a single semester.
Features:
"About this title" may belong to another edition of this title.
| Order quantity | 5 to 14 business days | 5 to 14 business days |
|---|---|---|
| First item | US$ 0.00 | US$ 14.00 |
Delivery times are set by sellers and vary by carrier and location. Orders passing through Customs may face delays and buyers are responsible for any associated duties or fees. Sellers may contact you regarding additional charges to cover any increased costs to ship your items.