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Debug Automation from Pre-Silicon to Post-Silicon.
Seller: Universitätsbuchhandlung Herta Hold GmbH, Berlin, Germany
Association Member: GIAQ ILAB VDA
Seller rating 5 out of 5 stars
XIV, 171 p. Hardcover. Versand aus Deutschland / We dispatch from Germany via Air Mail. Einband bestoßen, daher Mängelexemplar gestempelt, sonst sehr guter Zustand. Imperfect copy due to slightly bumped cover, apart from this in very good condition. Stamped. Stamped. Sprache: Englisch.
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Advanced BDD Optimization (Universitext)
Book 133 of 261: UniversitextSeller: Wonder Book, Frederick, MD, U.S.A.
Seller rating 5 out of 5 stars
Condition: Good. Good condition. A copy that has been read but remains intact. May contain markings such as bookplates, stamps, limited notes and highlighting, or a few light stains.
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Debug Automation from Pre-Silicon to Post-Silicon
Seller: Ria Christie Collections, Uxbridge, United Kingdom
Seller rating 5 out of 5 stars
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Brand new book. Fast ship. Please provide full street address as we are not able to ship to P O box address.
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Condition: Brand New. New. US edition. Expediting shipping for all USA and Europe orders excluding PO Box. Excellent Customer Service.
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Condition: New. This is a Brand-new US Edition. This Item may be shipped from US or any other country as we have multiple locations worldwide.
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Add to basketHardcover. Condition: Brand New. 2015 edition. 171 pages. 9.25x6.25x0.75 inches. In Stock.
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Debug Automation from Pre-Silicon to Post-Silicon
Language: English
Published by Springer International Publishing, 2016
ISBN 10: 3319356100 ISBN 13: 9783319356105
Taschenbuch. Condition: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book describes automated debugging approaches for the bugs and the faults which appear in different abstraction levels of a hardware system. The authors employ a transaction-based debug approach to systems at the transaction-level, asserting the correct relation of transactions. The automated debug approach for design bugs finds the potential fault candidates at RTL and gate-level of a circuit. Debug techniques for logic bugs and synchronization bugs are demonstrated, enabling readers to localize the most difficult bugs. Debug automation for electrical faults (delay faults)finds the potentially failing speedpaths in a circuit at gate-level. The various debug approaches described achieve high diagnosis accuracy and reduce the debugging time, shortening the IC development cycle and increasing the productivity of designers.Describes a unified framework for debug automation used at both pre-silicon and post-silicon stages;Provides approaches for debug automation of a hardware system at different levels of abstraction, i.e., chip, gate-level, RTL and transaction level;Includes techniques for debug automation of design bugs and electrical faults, as well as an infrastructure to debug NoC-based multiprocessor SoCs.
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Debug Automation from Pre-Silicon to Post-Silicon
Language: English
Published by Springer International Publishing, 2014
ISBN 10: 3319093088 ISBN 13: 9783319093086
Buch. Condition: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book describes automated debugging approaches for the bugs and the faults which appear in different abstraction levels of a hardware system. The authors employ a transaction-based debug approach to systems at the transaction-level, asserting the correct relation of transactions. The automated debug approach for design bugs finds the potential fault candidates at RTL and gate-level of a circuit. Debug techniques for logic bugs and synchronization bugs are demonstrated, enabling readers to localize the most difficult bugs. Debug automation for electrical faults (delay faults)finds the potentially failing speedpaths in a circuit at gate-level. The various debug approaches described achieve high diagnosis accuracy and reduce the debugging time, shortening the IC development cycle and increasing the productivity of designers.Describes a unified framework for debug automation used at both pre-silicon and post-silicon stages;Provides approaches for debug automation of a hardware system at different levels of abstraction, i.e., chip, gate-level, RTL and transaction level;Includes techniques for debug automation of design bugs and electrical faults, as well as an infrastructure to debug NoC-based multiprocessor SoCs.
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Test Pattern Generation using Boolean Proof Engines
Seller: Ria Christie Collections, Uxbridge, United Kingdom
Seller rating 5 out of 5 stars
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Robustness and Usability in Modern Design Flows
Seller: Ria Christie Collections, Uxbridge, United Kingdom
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Debug Automation from Pre-Silicon to Post-Silicon
Language: English
Published by Springer International Publishing, 2016
ISBN 10: 3319356100 ISBN 13: 9783319356105
Taschenbuch. Condition: Neu. Debug Automation from Pre-Silicon to Post-Silicon | Görschwin Fey (u. a.) | Taschenbuch | xiv | Englisch | 2016 | Springer International Publishing | EAN 9783319356105 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu.
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Brand new book. Fast ship. Please provide full street address as we are not able to ship to P O box address.
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Robustness and Usability in Modern Design Flows
Seller: Ria Christie Collections, Uxbridge, United Kingdom
Seller rating 5 out of 5 stars
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Add to basketPaperback. Condition: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.
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Advanced BDD Optimization
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Condition: Gut. Zustand: Gut | Sprache: Englisch | Produktart: Bücher | Keine Beschreibung verfügbar.
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Condition: Gut. Zustand: Gut | Sprache: Englisch | Produktart: Bücher | Keine Beschreibung verfügbar.
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Advanced BDD Optimization
Seller: Ria Christie Collections, Uxbridge, United Kingdom
Seller rating 5 out of 5 stars
US$ 188.28
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Condition: Hervorragend. Zustand: Hervorragend | Sprache: Englisch | Produktart: Bücher | After producing a chip, the functional correctness of the integrated circuit has to be checked. Otherwise products with malfunctions would be delivered to customers, which is not acceptable for any company. Many algorithms for "Automatic Test Pattern Generation" (ATPG) have been proposed in the last 30 years. But due to the ever increasing design complexity, new techniques have to be developed that can cope with today's circuits. While classical approaches are based on backtracking on the circuit structure, several approaches based on "Boolean Satisfiability" (SAT) have been proposed since the early 80s. In Test Pattern Generation using Boolean Proof Engines, we give an introduction to ATPG. The basic concept and classical ATPG algorithms are reviewed. Then, the formulation as a SAT problem is considered. As the underlying engine, modern SAT solvers and their use on circuit related problems are comprehensively discussed. Advanced techniques for SAT-based ATPG are introduced and evaluated in the context of an industrial environment. The chapters of the book cover efficient instance generation, encoding of multiple-valued logic, usage of various fault models, and detailed experiments on multi-million gate designs. The book describes the state of the art in the field, highlights research aspects, and shows directions for future work.
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Buch. Condition: Neu. Druck auf Anfrage Neuware - Printed after ordering - The size of technically producible integrated circuits increases continuously. But the ability to design and verify these circuits does not keep up with this development. Therefore, today's design ow has to be improved to achieve a higher productivity. In this book the current design methodology and ver- cation methodology are analyzed, a number of de ciencies are identi ed, and solutions are suggested. Improvements in the methodology as well as in the underlying algorithms are proposed. An in-depth presentation of preliminary concepts makes the book self-contained. Based on this foundation major - sign problems are targeted. In particular, a complete tool ow for Synthesis for Testability of SystemC descriptions is presented. The resulting circuits are completely testable and test pattern generation in polynomial time is possible. Veri cation issues are covered in even more detail. A whole new paradigm for formal design veri cation is suggested. This is based upon design und- standing, the automatic generation of properties, and powerful tool support for debugging failures. All these new techniques are empirically evaluated and - perimental results are provided. As a result, an enhanced design ow is created that provides more automation (i.e. better usability) and reduces the probability of introducing conceptual errors (i.e. higher robustness). Acknowledgments We would like to thank all members of the research group for computer arc- tecture in Bremen for the helpful discussions and the great atmosphere during work and research.
