Parvathi Muddapu (6 results)

Paperback. Condition: Brand New. 252 pages. 8.66x5.91x0.57 inches. In Stock.

Taschenbuch. Condition: Neu. TESTING OF eSRAM USING MMC- Algorithm And Parasitic Extraction Method | Muddapu Parvathi (u. a.) | Taschenbuch | 252 S. | Englisch | 2017 | LAP LAMBERT Academic Publishing | EAN 9786202095464 | Verantwortliche Person für die EU: BoD - Books on Demand, In de Tarpen 42, 22848 Norderstedt, info[at]bod[dot]de | Anbieter: preigu.

Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -The intention of the book is to highlight core issues of current technology relevant to embedded SRAM, testing methods and need of new test requirements. The importance of March algorithms and in depth working including examples were clearly shown. The failures of existing March algorithms and hence the development of MMC- (Modified March C-) algorithm will increase the reader interest in exploring much more test algorithms required for e-SRAM. Above this, the testing method using Parasitic extraction of R & C developed using Cadence tools and Microwind is highlight of the investigations. The layout level parasitic extraction of R&C method was applied on all possible SRAM fault models using 'bridge/short' created in electrical circuit environment. Using parasitic memory effect, fault detection dictionary was an outcome this research in which each fault model behavior is highlighted in terms of R & C at different technology nodes. The chosen technology nodes are 90nm, 120nm, and 180nm. This method was extended to few two cell fault models and discussed on coupling faults. 252 pp. Englisch.

Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Parvathi MuddapuDr. M. Parvathi,having 17 years of teaching experience, presently working as Professor in BVRITH College of Engineering for Women, have done her B.tech (ECE) from NIT Warangal, and M. Tech from JNTU Hyderabad. She ob.

Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -The intention of the book is to highlight core issues of current technology relevant to embedded SRAM, testing methods and need of new test requirements. The importance of March algorithms and in depth working including examples were clearly shown. The failures of existing March algorithms and hence the development of MMC- (Modified March C-) algorithm will increase the reader interest in exploring much more test algorithms required for e-SRAM. Above this, the testing method using Parasitic extraction of R & C developed using Cadence tools and Microwind is highlight of the investigations. The layout level parasitic extraction of R&C method was applied on all possible SRAM fault models using 'bridge/short' created in electrical circuit environment. Using parasitic memory effect, fault detection dictionary was an outcome this research in which each fault model behavior is highlighted in terms of R & C at different technology nodes. The chosen technology nodes are 90nm, 120nm, and 180nm. This method was extended to few two cell fault models and discussed on coupling faults.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 252 pp. Englisch.

Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - The intention of the book is to highlight core issues of current technology relevant to embedded SRAM, testing methods and need of new test requirements. The importance of March algorithms and in depth working including examples were clearly shown. The failures of existing March algorithms and hence the development of MMC- (Modified March C-) algorithm will increase the reader interest in exploring much more test algorithms required for e-SRAM. Above this, the testing method using Parasitic extraction of R & C developed using Cadence tools and Microwind is highlight of the investigations. The layout level parasitic extraction of R&C method was applied on all possible SRAM fault models using 'bridge/short' created in electrical circuit environment. Using parasitic memory effect, fault detection dictionary was an outcome this research in which each fault model behavior is highlighted in terms of R & C at different technology nodes. The chosen technology nodes are 90nm, 120nm, and 180nm. This method was extended to few two cell fault models and discussed on coupling faults.