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High Level Estimation Exploration Reliability by Wang Zheng (24 results)
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High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip.
Published by Singapore, Springer., 2018
ISBN 10: 9811093210 ISBN 13: 9789811093210
Language: English
Seller: Universitätsbuchhandlung Herta Hold GmbH, Berlin, Germany
Association Member: GIAQ ILAB VDA
Seller rating 5 out of 5 stars
US$ 14.47
Convert currencyUS$ 35.12 shipping from Germany to U.S.A.Quantity: 1 available
Add to basketXX, 197 p. Softcover. Versand aus Deutschland / We dispatch from Germany via Air Mail. Einband bestoßen, daher Mängelexemplar gestempelt, sonst sehr guter Zustand. Imperfect copy due to slightly bumped cover, apart from this in very good condition. Stamped. Computer Architecture and Design Methodologies. Sprache: Englisch.
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Condition: New.
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US$ 116.06
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Condition: New.
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US$ 116.44
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Condition: As New. Unread book in perfect condition.
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Condition: As New. Unread book in perfect condition.
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High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip (Paperback)
Published by Springer Verlag, Singapore, Singapore, 2018
ISBN 10: 9811093210 ISBN 13: 9789811093210
Language: English
Paperback. Condition: new. Paperback. This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures. This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. Shipping may be from multiple locations in the US or from the UK, depending on stock availability.
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High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip (Computer Architecture and Design Methodologies)
Seller: Ria Christie Collections, Uxbridge, United Kingdom
Seller rating 5 out of 5 stars
US$ 129.99
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Add to basketCondition: New. In.
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Condition: New.
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High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip (Hardcover)
Published by Springer Verlag, Singapore, Singapore, 2017
ISBN 10: 9811010722 ISBN 13: 9789811010729
Language: English
First Edition
Hardcover. Condition: new. Hardcover. This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures. This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. Shipping may be from multiple locations in the US or from the UK, depending on stock availability.
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High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip (Computer Architecture and Design Methodologies)
Seller: Ria Christie Collections, Uxbridge, United Kingdom
Seller rating 5 out of 5 stars
US$ 134.81
Convert currencyUS$ 16.06 shipping from United Kingdom to U.S.A.Quantity: Over 20 available
Add to basketCondition: New. In.
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Condition: New. pp. 217.
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US$ 111.25
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US$ 111.25
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US$ 176.32
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Add to basketPaperback. Condition: Brand New. reprint edition. 197 pages. 9.25x6.10x0.47 inches. In Stock.
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US$ 178.64
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Add to basketHardcover. Condition: Brand New. 217 pages. 9.25x6.10x0.56 inches. In Stock.
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Condition: New.
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High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip (Paperback)
Published by Springer Verlag, Singapore, Singapore, 2018
ISBN 10: 9811093210 ISBN 13: 9789811093210
Language: English
US$ 300.72
Convert currencyUS$ 37.00 shipping from Australia to U.S.A.Quantity: 1 available
Add to basketPaperback. Condition: new. Paperback. This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures. This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. Shipping may be from our Sydney, NSW warehouse or from our UK or US warehouse, depending on stock availability.
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High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip (Hardcover)
Published by Springer Verlag, Singapore, Singapore, 2017
ISBN 10: 9811010722 ISBN 13: 9789811010729
Language: English
First Edition
US$ 331.83
Convert currencyUS$ 37.00 shipping from Australia to U.S.A.Quantity: 1 available
Add to basketHardcover. Condition: new. Hardcover. This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures. This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. Shipping may be from our Sydney, NSW warehouse or from our UK or US warehouse, depending on stock availability.
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US$ 162.34
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Add to basketCondition: New. Print on Demand pp. 217.
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US$ 176.37
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Add to basketCondition: New. PRINT ON DEMAND pp. 217.
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US$ 222.78
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US$ 249.96
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Add to basketCondition: New. PRINT ON DEMAND.
